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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [spi_model/] [rtl/] [xml/] [spi_model_master.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
spi_model
master
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      spi_model_master
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      spi_model_master
    
  

 
 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/spi_model_master
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.master.rtl
        verilogSourcefragment
      
 
      
        
        ../verilog/top.master.tasks
        verilogSourcefragment
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/spi_model_master
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.master.rtl
        verilogSourcefragment
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
 
 
 
 
 
  
 
 
 

 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
  
 
              
              Hierarchical
                  Hierarchical
              
 
 
 
 
             
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 

CLKCNT10'h1f0
SIZE10

 

 
clk
wire
in

 
reset
wire
in

 
 
spi_clk
reg
out

 
spi_mosi
reg
out

 
spi_miso
wire
in

 
spi_sel_n
reg
out

 
 

 

 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [spi_model/] [rtl/] [xml/] [spi_model_master.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`spi_model`
40			`master`
41
42
43
44
45			`gen_verilog_sim`
46			`104.0`
47			`none`
48			`:Simulation:`
49			`tools/verilog/gen_verilog`
50
51
52			`destination`
53			`spi_model_master`
54
55
56
57
58
59
60			`gen_verilog_syn`
61			`104.0`
62			`none`
63			`:Synthesis:`
64			`tools/verilog/gen_verilog`
65
66
67			`destination`
68			`spi_model_master`
69
70
71
72
73
74
75
76
77
78
79
80
81
82			`fs-sim`
83
84
85
86			`../verilog/copyright`
87			`verilogSourceinclude`
88
89
90
91
92			`../verilog/sim/spi_model_master`
93			`verilogSourcemodule`
94
95
96
97
98
99			`../verilog/top.master.rtl`
100			`verilogSourcefragment`
101
102
103
104
105			`../verilog/top.master.tasks`
106			`verilogSourcefragment`
107
108
109
110			`dest_dir../views/sim/`
111			`verilogSourcelibraryDir`
112
113
114
115
116
117
118
119
120
121
122
123
124			`fs-syn`
125
126
127
128			`../verilog/copyright`
129			`verilogSourceinclude`
130
131
132
133
134
135			`../verilog/syn/spi_model_master`
136			`verilogSourcemodule`
137
138
139
140
141
142			`../verilog/top.master.rtl`
143			`verilogSourcefragment`
144
145
146
147			`dest_dir../views/syn/`
148			`verilogSourcelibraryDir`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170			`Hierarchical`
171
172
173
174
175
176
177
178
179
180
181			`Hierarchical`
182			`Hierarchical`
183
184
185
186
187
188
189			`verilog`
190
191
192			`ipxact:library="Testbench"`
193			`ipxact:name="toolflow"`
194			`ipxact:version="verilog"/>`
195
196
197
198
199
200
201
202
203
204			`sim:Simulation:`
205
206			`Verilog`
207
208
209			`fs-sim`
210
211
212
213
214			`syn:Synthesis:`
215
216			`Verilog`
217
218
219			`fs-syn`
220
221
222
223
224			`doc`
225
226
227			`ipxact:library="Testbench"`
228			`ipxact:name="toolflow"`
229			`ipxact:version="documentation"/>`
230
231			`:Documentation:`
232			`Verilog`
233
234
235
236
237
238
239
240			`CLKCNT10'h1f0`
241			`SIZE10`
242
243
244
245
246			`clk`
247			`wire`
248			`in`
249
250
251			`reset`
252			`wire`
253			`in`
254
255
256
257			`spi_clk`
258			`reg`
259			`out`
260
261
262			`spi_mosi`
263			`reg`
264			`out`
265
266
267			`spi_miso`
268			`wire`
269			`in`
270
271
272			`spi_sel_n`
273			`reg`
274			`out`
275
276
277
278
279
280
281
282
283
284