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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [verilog/] [code] - Blame information for rev 134

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Line No. Rev Author Line
1 134 jt_eaton
assign drive_8 = 8'bzzzzzzzz;
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assign drive_1 = 1'bz;
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always@(posedge clk)
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if(reset)
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  begin
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  parity_enable         <= 1'b0;
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  txd_data_in           <= 8'h00;
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  txd_parity            <= 1'b0;
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  txd_force_parity      <= 1'b0;
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  txd_load              <= 1'b0;
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  txd_break             <= 1'b0;
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  rxd_parity            <= 1'b0;
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  rxd_force_parity      <= 1'b0;
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  rxd_data_avail_stb    <= 1'b0;
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  exp_rxd_stop_error    <= 1'b0;
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  exp_rxd_parity_error  <= 1'b0;
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  exp_rxd_data_out      <= 8'h00;
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  mask_rxd_stop_error   <= 1'b0;
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  mask_rxd_parity_error <= 1'b0;
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  mask_rxd_data_out     <= 8'h00;
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  end
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