OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [verilog/] [tasks] - Blame information for rev 134

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 134 jt_eaton
 
2
 
3
 
4
task automatic next;
5
  input [31:0] num;
6
  repeat (num)       @ (posedge clk);
7
endtask
8
 
9
 
10
 
11
 
12
task clear_rx_host;
13
 begin
14
 next(1);
15
 end
16
endtask
17
 
18
 
19
 
20
 
21
task send_byte;
22
  input [7:0] byte_out;
23
 
24
   begin
25
   while(!txd_buffer_empty)   next(1);
26
   $display("%t %m         %2h",$realtime ,byte_out);
27
   txd_data_in  <= byte_out;
28
   next(1);
29
   txd_load   <= 1'b1;
30
   next(1);
31
   txd_load   <= 1'b0;
32
   next(1);
33
   end
34
endtask // send_byte
35
 
36
 
37
 
38
task rcv_byte;
39
  input [7:0] byte_in;
40
   begin
41
   exp_rxd_data_out     <= byte_in;
42
   while(!rxd_data_avail)  next(1);
43
   $display("%t %m checking %h",$realtime,byte_in);
44
   mask_rxd_stop_error   <= 1'b1;
45
   mask_rxd_parity_error <= 1'b1;
46
   mask_rxd_data_out     <= 8'hff;
47
   next(1);
48
   mask_rxd_stop_error   <= 1'b0;
49
   mask_rxd_parity_error <= 1'b0;
50
   mask_rxd_data_out     <= 8'h00;
51
   rxd_data_avail_stb   <= 1'b1;
52
   next(1);
53
   rxd_data_avail_stb   <= 1'b0;
54
   next(1);
55
end
56
endtask
57
 
58
 
59
 
60
 

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.