OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [verilog/] [top.sim] - Blame information for rev 134

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 131 jt_eaton
 
2
/**********************************************************************/
3
/*                                                                    */
4
/*             -------                                                */
5
/*            /   SOC  \                                              */
6
/*           /    GEN   \                                             */
7
/*          /     SIM    \                                            */
8
/*          ==============                                            */
9
/*          |            |                                            */
10
/*          |____________|                                            */
11
/*                                                                    */
12
/*  uart host model for simulations                                   */
13
/*                                                                    */
14
/*                                                                    */
15
/*  Author(s):                                                        */
16
/*      - John Eaton, jt_eaton@opencores.org                          */
17
/*                                                                    */
18
/**********************************************************************/
19
/*                                                                    */
20
/*    Copyright (C) <2010>                     */
21
/*                                                                    */
22
/*  This source file may be used and distributed without              */
23
/*  restriction provided that this copyright statement is not         */
24
/*  removed from the file and that any derivative work contains       */
25
/*  the original copyright notice and the associated disclaimer.      */
26
/*                                                                    */
27
/*  This source file is free software; you can redistribute it        */
28
/*  and/or modify it under the terms of the GNU Lesser General        */
29
/*  Public License as published by the Free Software Foundation;      */
30
/*  either version 2.1 of the License, or (at your option) any        */
31
/*  later version.                                                    */
32
/*                                                                    */
33
/*  This source is distributed in the hope that it will be            */
34
/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
35
/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
36
/*  PURPOSE.  See the GNU Lesser General Public License for more      */
37
/*  details.                                                          */
38
/*                                                                    */
39
/*  You should have received a copy of the GNU Lesser General         */
40
/*  Public License along with this source; if not, download it        */
41
/*  from http://www.opencores.org/lgpl.shtml                          */
42
/*                                                                    */
43
/**********************************************************************/
44
 
45
 
46
 
47
module uart_host_def (
48
input  wire           clk,
49
input  wire           reset,
50 134 jt_eaton
input  wire           rxd_data_avail,
51
input  wire           rxd_stop_error,
52
input  wire           rxd_parity_error,
53
input  wire           txd_buffer_empty,
54
input  wire [7:0]     rxd_data_out,
55
output  reg           parity_enable,
56
output  reg           rxd_data_avail_stb,
57
output  reg           rxd_force_parity,
58
output  reg           rxd_parity,
59
output  reg           txd_break,
60 131 jt_eaton
output  reg           txd_force_parity,
61
output  reg           txd_load,
62 134 jt_eaton
output  reg           txd_parity,
63
output  reg [7:0]     txd_data_in
64
 
65 131 jt_eaton
);
66
 
67 134 jt_eaton
reg       exp_rxd_stop_error;
68
reg       exp_rxd_parity_error;
69 131 jt_eaton
reg [7:0] exp_rxd_data_out;
70
 
71 134 jt_eaton
reg       mask_rxd_stop_error;
72
reg       mask_rxd_parity_error;
73 131 jt_eaton
reg [7:0] mask_rxd_data_out;
74
 
75
 
76
 
77
 
78 134 jt_eaton
io_probe_in
79
#(.MESG("uart_host receive error"),
80
  .WIDTH(8))
81
rxd_data_out_prb
82
(
83
       .clk            ( clk               ),
84
       .expected_value ( exp_rxd_data_out  ),
85
       .mask           ( mask_rxd_data_out ),
86
       .signal         ( rxd_data_out      )
87
);
88
 
89
io_probe_in
90
#(.MESG("uart_host stop error"))
91
rxd_stop_error_prb
92
(
93
       .clk            ( clk                 ),
94
       .expected_value ( exp_rxd_stop_error  ),
95
       .mask           ( mask_rxd_stop_error ),
96
       .signal         ( rxd_stop_error      )
97
);
98
 
99
 
100
 
101
 
102
io_probe_in
103
#(.MESG("uart_host parity error"))
104
rxd_parity_error_prb
105
(
106
       .clk            ( clk                   ),
107
       .expected_value ( exp_rxd_parity_error  ),
108
       .mask           ( mask_rxd_parity_error ),
109
       .signal         ( rxd_parity_error      )
110
 
111
 
112
);
113
 
114 131 jt_eaton
 
115
always@(posedge clk)
116
if(reset)
117
  begin
118
  parity_enable        <= 1'b0;
119
  txd_data_in          <= 8'h00;
120
  txd_parity           <= 1'b0;
121
  txd_force_parity     <= 1'b0;
122
  txd_load             <= 1'b0;
123
  txd_break            <= 1'b0;
124
  rxd_parity           <= 1'b0;
125
  rxd_force_parity     <= 1'b0;
126
  rxd_data_avail_stb   <= 1'b0;
127
  exp_rxd_stop_error   <= 1'b0;
128
  exp_rxd_parity_error <= 1'b0;
129
  exp_rxd_data_out     <= 8'h00;
130
 
131
  mask_rxd_stop_error   <= 1'b0;
132
  mask_rxd_parity_error <= 1'b0;
133
  mask_rxd_data_out     <= 8'h00;
134
 
135
 
136
 end
137
 
138
 
139 134 jt_eaton
 
140
 
141
 
142
task automatic next;
143
  input [31:0] num;
144
  repeat (num)       @ (posedge clk);
145
endtask
146
 
147
 
148
 
149
 
150 131 jt_eaton
task clear_rx_host;
151
 begin
152
 next(1);
153
 end
154
endtask
155
 
156
 
157
 
158
 
159
task send_byte;
160
  input [7:0] byte_out;
161
 
162
   begin
163
   while(!txd_buffer_empty)   next(1);
164
   $display("%t %m         %2h",$realtime ,byte_out);
165
   txd_data_in  <= byte_out;
166
   next(1);
167
   txd_load   <= 1'b1;
168
   next(1);
169
   txd_load   <= 1'b0;
170
   next(1);
171
   end
172
endtask // send_byte
173
 
174
 
175
 
176
task rcv_byte;
177
  input [7:0] byte_in;
178
   begin
179
   exp_rxd_data_out     <= byte_in;
180
   while(!rxd_data_avail)  next(1);
181
   $display("%t %m checking %h",$realtime,byte_in);
182
   mask_rxd_stop_error   <= 1'b1;
183
   mask_rxd_parity_error <= 1'b1;
184
   mask_rxd_data_out     <= 8'hff;
185
   next(1);
186
   mask_rxd_stop_error   <= 1'b0;
187
   mask_rxd_parity_error <= 1'b0;
188
   mask_rxd_data_out     <= 8'h00;
189
   rxd_data_avail_stb   <= 1'b1;
190
   next(1);
191
   rxd_data_avail_stb   <= 1'b0;
192
   next(1);
193
end
194
endtask
195
 
196
 
197
endmodule
198
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.