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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [verilog/] [top.sim] - Blame information for rev 134

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1 131 jt_eaton 
 
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/**********************************************************************/
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/*                                                                    */
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/*             -------                                                */
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/*            /   SOC  \                                              */
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/*           /    GEN   \                                             */
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/*          /     SIM    \                                            */
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/*          ==============                                            */
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/*          |            |                                            */
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/*          |____________|                                            */
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/*                                                                    */
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/*  uart host model for simulations                                   */
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/*                                                                    */
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/*                                                                    */
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/*  Author(s):                                                        */
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/*      - John Eaton, jt_eaton@opencores.org                          */
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/*                                                                    */
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/**********************************************************************/
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/*                                                                    */
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/*    Copyright (C) <2010>                     */
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/*                                                                    */
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/*  This source file may be used and distributed without              */
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/*  restriction provided that this copyright statement is not         */
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/*  removed from the file and that any derivative work contains       */
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/*  the original copyright notice and the associated disclaimer.      */
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/*                                                                    */
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/*  This source file is free software; you can redistribute it        */
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/*  and/or modify it under the terms of the GNU Lesser General        */
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/*  Public License as published by the Free Software Foundation;      */
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/*  either version 2.1 of the License, or (at your option) any        */
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/*  later version.                                                    */
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/*                                                                    */
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/*  This source is distributed in the hope that it will be            */
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/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
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/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
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/*  PURPOSE.  See the GNU Lesser General Public License for more      */
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/*  details.                                                          */
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/*                                                                    */
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/*  You should have received a copy of the GNU Lesser General         */
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/*  Public License along with this source; if not, download it        */
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/*  from http://www.opencores.org/lgpl.shtml                          */
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/*                                                                    */
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/**********************************************************************/
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module uart_host_def (
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input  wire           clk,
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input  wire           reset,
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input  wire           rxd_data_avail,
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input  wire           rxd_stop_error,
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input  wire           rxd_parity_error,
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input  wire           txd_buffer_empty,
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input  wire [7:0]     rxd_data_out,
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output  reg           parity_enable,
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output  reg           rxd_data_avail_stb,
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output  reg           rxd_force_parity,
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output  reg           rxd_parity,
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output  reg           txd_break,
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output  reg           txd_force_parity,
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output  reg           txd_load,
62 134 jt_eaton 
output  reg           txd_parity,
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output  reg [7:0]     txd_data_in
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65 131 jt_eaton 
);
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67 134 jt_eaton 
reg       exp_rxd_stop_error;
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reg       exp_rxd_parity_error;
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reg [7:0] exp_rxd_data_out;
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71 134 jt_eaton 
reg       mask_rxd_stop_error;
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reg       mask_rxd_parity_error;
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reg [7:0] mask_rxd_data_out;
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78 134 jt_eaton 
io_probe_in
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#(.MESG("uart_host receive error"),
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  .WIDTH(8))
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rxd_data_out_prb
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(
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       .clk            ( clk               ),
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       .expected_value ( exp_rxd_data_out  ),
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       .mask           ( mask_rxd_data_out ),
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       .signal         ( rxd_data_out      )
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);
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io_probe_in
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#(.MESG("uart_host stop error"))
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rxd_stop_error_prb
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(
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       .clk            ( clk                 ),
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       .expected_value ( exp_rxd_stop_error  ),
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       .mask           ( mask_rxd_stop_error ),
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       .signal         ( rxd_stop_error      )
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);
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io_probe_in
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#(.MESG("uart_host parity error"))
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rxd_parity_error_prb
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(
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       .clk            ( clk                   ),
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       .expected_value ( exp_rxd_parity_error  ),
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       .mask           ( mask_rxd_parity_error ),
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       .signal         ( rxd_parity_error      )
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);
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always@(posedge clk)
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if(reset)
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  begin
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  parity_enable        <= 1'b0;
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  txd_data_in          <= 8'h00;
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  txd_parity           <= 1'b0;
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  txd_force_parity     <= 1'b0;
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  txd_load             <= 1'b0;
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  txd_break            <= 1'b0;
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  rxd_parity           <= 1'b0;
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  rxd_force_parity     <= 1'b0;
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  rxd_data_avail_stb   <= 1'b0;
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  exp_rxd_stop_error   <= 1'b0;
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  exp_rxd_parity_error <= 1'b0;
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  exp_rxd_data_out     <= 8'h00;
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  mask_rxd_stop_error   <= 1'b0;
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  mask_rxd_parity_error <= 1'b0;
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  mask_rxd_data_out     <= 8'h00;
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 end
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139 134 jt_eaton 
 
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task automatic next;
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  input [31:0] num;
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  repeat (num)       @ (posedge clk);
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endtask
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150 131 jt_eaton 
task clear_rx_host;
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 begin
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 next(1);
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 end
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endtask
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task send_byte;
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  input [7:0] byte_out;
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   begin
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   while(!txd_buffer_empty)   next(1);
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   $display("%t %m         %2h",$realtime ,byte_out);
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   txd_data_in  <= byte_out;
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   next(1);
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   txd_load   <= 1'b1;
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   next(1);
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   txd_load   <= 1'b0;
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   next(1);
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   end
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endtask // send_byte
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task rcv_byte;
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  input [7:0] byte_in;
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   begin
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   exp_rxd_data_out     <= byte_in;
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   while(!rxd_data_avail)  next(1);
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   $display("%t %m checking %h",$realtime,byte_in);
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   mask_rxd_stop_error   <= 1'b1;
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   mask_rxd_parity_error <= 1'b1;
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   mask_rxd_data_out     <= 8'hff;
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   next(1);
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   mask_rxd_stop_error   <= 1'b0;
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   mask_rxd_parity_error <= 1'b0;
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   mask_rxd_data_out     <= 8'h00;
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   rxd_data_avail_stb   <= 1'b1;
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   next(1);
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   rxd_data_avail_stb   <= 1'b0;
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   next(1);
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end
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endtask
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endmodule
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