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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [verilog/] [top.sim] - Blame information for rev 131

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/**********************************************************************/
/*                                                                    */
/*             -------                                                */
/*            /   SOC  \                                              */
/*           /    GEN   \                                             */
/*          /     SIM    \                                            */
/*          ==============                                            */
/*          |            |                                            */
/*          |____________|                                            */
/*                                                                    */
/*  uart host model for simulations                                   */
/*                                                                    */
/*                                                                    */
/*  Author(s):                                                        */
/*      - John Eaton, jt_eaton@opencores.org                          */
/*                                                                    */
/**********************************************************************/
/*                                                                    */
/*    Copyright (C) <2010>                     */
/*                                                                    */
/*  This source file may be used and distributed without              */
/*  restriction provided that this copyright statement is not         */
/*  removed from the file and that any derivative work contains       */
/*  the original copyright notice and the associated disclaimer.      */
/*                                                                    */
/*  This source file is free software; you can redistribute it        */
/*  and/or modify it under the terms of the GNU Lesser General        */
/*  Public License as published by the Free Software Foundation;      */
/*  either version 2.1 of the License, or (at your option) any        */
/*  later version.                                                    */
/*                                                                    */
/*  This source is distributed in the hope that it will be            */
/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
/*  PURPOSE.  See the GNU Lesser General Public License for more      */
/*  details.                                                          */
/*                                                                    */
/*  You should have received a copy of the GNU Lesser General         */
/*  Public License along with this source; if not, download it        */
/*  from http://www.opencores.org/lgpl.shtml                          */
/*                                                                    */
/**********************************************************************/
 
 
 
module uart_host_def (
input  wire           clk,
input  wire           reset,
output reg            parity_enable,
output  reg           txd_parity,
output  reg           txd_force_parity,
output  reg [7:0]     txd_data_in,
input  wire           txd_buffer_empty,
output  reg           txd_load,
output  reg           txd_break,
output  reg           rxd_parity,
output  reg           rxd_force_parity,
output  reg           rxd_data_avail_stb,
inout  wire [7:0]     rxd_data_out,
input  wire           rxd_data_avail,
inout  wire           rxd_stop_error,
inout  wire           rxd_parity_error
);
 
reg exp_rxd_stop_error;
reg exp_rxd_parity_error;
reg [7:0] exp_rxd_data_out;
 
reg mask_rxd_stop_error;
reg mask_rxd_parity_error;
reg [7:0] mask_rxd_data_out;
 
 
 
 
 
task automatic next;
  input [31:0] num;
  repeat (num)       @ (posedge clk);
endtask
 
 
 
always@(posedge clk)
if(reset)
  begin
  parity_enable        <= 1'b0;
  txd_data_in          <= 8'h00;
  txd_parity           <= 1'b0;
  txd_force_parity     <= 1'b0;
  txd_load             <= 1'b0;
  txd_break            <= 1'b0;
  rxd_parity           <= 1'b0;
  rxd_force_parity     <= 1'b0;
  rxd_data_avail_stb   <= 1'b0;
  exp_rxd_stop_error   <= 1'b0;
  exp_rxd_parity_error <= 1'b0;
  exp_rxd_data_out     <= 8'h00;
 
  mask_rxd_stop_error   <= 1'b0;
  mask_rxd_parity_error <= 1'b0;
  mask_rxd_data_out     <= 8'h00;
 
 
 end
 
 
task clear_rx_host;
 begin
 next(1);
 end
endtask
 
 
 
 
task send_byte;
  input [7:0] byte_out;
 
   begin
   while(!txd_buffer_empty)   next(1);
   $display("%t %m         %2h",$realtime ,byte_out);
   txd_data_in  <= byte_out;
   next(1);
   txd_load   <= 1'b1;
   next(1);
   txd_load   <= 1'b0;
   next(1);
   end
endtask // send_byte
 
 
 
task rcv_byte;
  input [7:0] byte_in;
   begin
   exp_rxd_data_out     <= byte_in;
   while(!rxd_data_avail)  next(1);
   $display("%t %m checking %h",$realtime,byte_in);
   mask_rxd_stop_error   <= 1'b1;
   mask_rxd_parity_error <= 1'b1;
   mask_rxd_data_out     <= 8'hff;
   next(1);
   mask_rxd_stop_error   <= 1'b0;
   mask_rxd_parity_error <= 1'b0;
   mask_rxd_data_out     <= 8'h00;
   rxd_data_avail_stb   <= 1'b1;
   next(1);
   rxd_data_avail_stb   <= 1'b0;
   next(1);
end
endtask
 
 
io_probe_def
#(.MESG("uart_host receive error"),
  .WIDTH(8))
rxd_data_out_prb
(
       .clk            ( clk               ),
       .drive_value    (8'bzzzzzzzz        ),
       .expected_value ( exp_rxd_data_out  ),
       .mask           ( mask_rxd_data_out ),
       .signal         ( rxd_data_out      )
 
 
);
 
 
 
 
 
 
io_probe_def
#(.MESG("uart_host stop error"))
rxd_stop_error_prb
(
       .clk            ( clk                 ),
       .drive_value    (1'bz                 ),
       .expected_value ( exp_rxd_stop_error  ),
       .mask           ( mask_rxd_stop_error ),
       .signal         ( rxd_stop_error      )
 
 
);
 
 
 
 
io_probe_def
#(.MESG("uart_host parity error"))
rxd_parity_error_prb
(
       .clk            ( clk                 ),
       .drive_value    (1'bz                 ),
       .expected_value ( exp_rxd_parity_error  ),
       .mask           ( mask_rxd_parity_error ),
       .signal         ( rxd_parity_error      )
 
 
);
 
 
 
 
 
 
 
endmodule
 

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [verilog/] [top.sim] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`/**********************************************************************/`
3			`/* */`
4			`/* ------- */`
5			`/* / SOC \ */`
6			`/* / GEN \ */`
7			`/* / SIM \ */`
8			`/* ============== */`
9			`/* \| \| */`
10			`/* \|____________\| */`
11			`/* */`
12			`/* uart host model for simulations */`
13			`/* */`
14			`/* */`
15			`/* Author(s): */`
16			`/* - John Eaton, jt_eaton@opencores.org */`
17			`/* */`
18			`/**********************************************************************/`
19			`/* */`
20			`/* Copyright (C) <2010> */`
21			`/* */`
22			`/* This source file may be used and distributed without */`
23			`/* restriction provided that this copyright statement is not */`
24			`/* removed from the file and that any derivative work contains */`
25			`/* the original copyright notice and the associated disclaimer. */`
26			`/* */`
27			`/* This source file is free software; you can redistribute it */`
28			`/* and/or modify it under the terms of the GNU Lesser General */`
29			`/* Public License as published by the Free Software Foundation; */`
30			`/* either version 2.1 of the License, or (at your option) any */`
31			`/* later version. */`
32			`/* */`
33			`/* This source is distributed in the hope that it will be */`
34			`/* useful, but WITHOUT ANY WARRANTY; without even the implied */`
35			`/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */`
36			`/* PURPOSE. See the GNU Lesser General Public License for more */`
37			`/* details. */`
38			`/* */`
39			`/* You should have received a copy of the GNU Lesser General */`
40			`/* Public License along with this source; if not, download it */`
41			`/* from http://www.opencores.org/lgpl.shtml */`
42			`/* */`
43			`/**********************************************************************/`
44
45
46
47			`module uart_host_def (`
48			`input wire clk,`
49			`input wire reset,`
50			`output reg parity_enable,`
51			`output reg txd_parity,`
52			`output reg txd_force_parity,`
53			`output reg [7:0] txd_data_in,`
54			`input wire txd_buffer_empty,`
55			`output reg txd_load,`
56			`output reg txd_break,`
57			`output reg rxd_parity,`
58			`output reg rxd_force_parity,`
59			`output reg rxd_data_avail_stb,`
60			`inout wire [7:0] rxd_data_out,`
61			`input wire rxd_data_avail,`
62			`inout wire rxd_stop_error,`
63			`inout wire rxd_parity_error`
64			`);`
65
66			`reg exp_rxd_stop_error;`
67			`reg exp_rxd_parity_error;`
68			`reg [7:0] exp_rxd_data_out;`
69
70			`reg mask_rxd_stop_error;`
71			`reg mask_rxd_parity_error;`
72			`reg [7:0] mask_rxd_data_out;`
73
74
75
76
77
78			`task automatic next;`
79			`input [31:0] num;`
80			`repeat (num) @ (posedge clk);`
81			`endtask`
82
83
84
85			`always@(posedge clk)`
86			`if(reset)`
87			`begin`
88			`parity_enable <= 1'b0;`
89			`txd_data_in <= 8'h00;`
90			`txd_parity <= 1'b0;`
91			`txd_force_parity <= 1'b0;`
92			`txd_load <= 1'b0;`
93			`txd_break <= 1'b0;`
94			`rxd_parity <= 1'b0;`
95			`rxd_force_parity <= 1'b0;`
96			`rxd_data_avail_stb <= 1'b0;`
97			`exp_rxd_stop_error <= 1'b0;`
98			`exp_rxd_parity_error <= 1'b0;`
99			`exp_rxd_data_out <= 8'h00;`
100
101			`mask_rxd_stop_error <= 1'b0;`
102			`mask_rxd_parity_error <= 1'b0;`
103			`mask_rxd_data_out <= 8'h00;`
104
105
106			`end`
107
108
109			`task clear_rx_host;`
110			`begin`
111			`next(1);`
112			`end`
113			`endtask`
114
115
116
117
118			`task send_byte;`
119			`input [7:0] byte_out;`
120
121			`begin`
122			`while(!txd_buffer_empty) next(1);`
123			`$display("%t %m %2h",$realtime ,byte_out);`
124			`txd_data_in <= byte_out;`
125			`next(1);`
126			`txd_load <= 1'b1;`
127			`next(1);`
128			`txd_load <= 1'b0;`
129			`next(1);`
130			`end`
131			`endtask // send_byte`
132
133
134
135			`task rcv_byte;`
136			`input [7:0] byte_in;`
137			`begin`
138			`exp_rxd_data_out <= byte_in;`
139			`while(!rxd_data_avail) next(1);`
140			`$display("%t %m checking %h",$realtime,byte_in);`
141			`mask_rxd_stop_error <= 1'b1;`
142			`mask_rxd_parity_error <= 1'b1;`
143			`mask_rxd_data_out <= 8'hff;`
144			`next(1);`
145			`mask_rxd_stop_error <= 1'b0;`
146			`mask_rxd_parity_error <= 1'b0;`
147			`mask_rxd_data_out <= 8'h00;`
148			`rxd_data_avail_stb <= 1'b1;`
149			`next(1);`
150			`rxd_data_avail_stb <= 1'b0;`
151			`next(1);`
152			`end`
153			`endtask`
154
155
156			`io_probe_def`
157			`#(.MESG("uart_host receive error"),`
158			`.WIDTH(8))`
159			`rxd_data_out_prb`
160			`(`
161			`.clk ( clk ),`
162			`.drive_value (8'bzzzzzzzz ),`
163			`.expected_value ( exp_rxd_data_out ),`
164			`.mask ( mask_rxd_data_out ),`
165			`.signal ( rxd_data_out )`
166
167
168			`);`
169
170
171
172
173
174
175			`io_probe_def`
176			`#(.MESG("uart_host stop error"))`
177			`rxd_stop_error_prb`
178			`(`
179			`.clk ( clk ),`
180			`.drive_value (1'bz ),`
181			`.expected_value ( exp_rxd_stop_error ),`
182			`.mask ( mask_rxd_stop_error ),`
183			`.signal ( rxd_stop_error )`
184
185
186			`);`
187
188
189
190
191			`io_probe_def`
192			`#(.MESG("uart_host parity error"))`
193			`rxd_parity_error_prb`
194			`(`
195			`.clk ( clk ),`
196			`.drive_value (1'bz ),`
197			`.expected_value ( exp_rxd_parity_error ),`
198			`.mask ( mask_rxd_parity_error ),`
199			`.signal ( rxd_parity_error )`
200
201
202			`);`
203
204
205
206
207
208
209
210			`endmodule`
211