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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [verilog/] [top.syn] - Blame information for rev 134

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/**********************************************************************/
/*                                                                    */
/*             -------                                                */
/*            /   SOC  \                                              */
/*           /    GEN   \                                             */
/*          /     SIM    \                                            */
/*          ==============                                            */
/*          |            |                                            */
/*          |____________|                                            */
/*                                                                    */
/*  uart host model for simulations                                   */
/*                                                                    */
/*                                                                    */
/*  Author(s):                                                        */
/*      - John Eaton, jt_eaton@opencores.org                          */
/*                                                                    */
/**********************************************************************/
/*                                                                    */
/*    Copyright (C) <2010>  <Ouabache Design Works>                   */
/*                                                                    */
/*  This source file may be used and distributed without              */
/*  restriction provided that this copyright statement is not         */
/*  removed from the file and that any derivative work contains       */
/*  the original copyright notice and the associated disclaimer.      */
/*                                                                    */
/*  This source file is free software; you can redistribute it        */
/*  and/or modify it under the terms of the GNU Lesser General        */
/*  Public License as published by the Free Software Foundation;      */
/*  either version 2.1 of the License, or (at your option) any        */
/*  later version.                                                    */
/*                                                                    */
/*  This source is distributed in the hope that it will be            */
/*  useful, but WITHOUT ANY WARRANTY; without even the implied        */
/*  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR           */
/*  PURPOSE.  See the GNU Lesser General Public License for more      */
/*  details.                                                          */
/*                                                                    */
/*  You should have received a copy of the GNU Lesser General         */
/*  Public License along with this source; if not, download it        */
/*  from http://www.opencores.org/lgpl.shtml                          */
/*                                                                    */
/**********************************************************************/
 
 
 
module uart_host_def (
input  wire           clk,
input  wire           reset,
output reg            parity_enable,
output  reg           txd_parity,
output  reg           txd_force_parity,
output  reg [7:0]     txd_data_in,
input  wire           txd_buffer_empty,
output  reg           txd_load,
output  reg           txd_break,
output  reg           rxd_parity,
output  reg           rxd_force_parity,
output  reg           rxd_data_avail_stb,
input  wire [7:0]     rxd_data_out,
input  wire           rxd_data_avail,
input  wire           rxd_stop_error,
input  wire           rxd_parity_error
);
 
reg exp_rxd_stop_error;
reg exp_rxd_parity_error;
reg [7:0] exp_rxd_data_out;
 
reg mask_rxd_stop_error;
reg mask_rxd_parity_error;
reg [7:0] mask_rxd_data_out;
 
 
 
io_probe_in
#(.MESG("uart_host receive error"),
  .WIDTH(8))
rxd_data_out_prb
(
       .clk            ( clk               ),
       .expected_value ( exp_rxd_data_out  ),
       .mask           ( mask_rxd_data_out ),
       .signal         ( rxd_data_out      )
 
 
);
 
 
 
 
 
 
io_probe_in
#(.MESG("uart_host stop error"))
rxd_stop_error_prb
(
       .clk            ( clk                 ),
       .expected_value ( exp_rxd_stop_error  ),
       .mask           ( mask_rxd_stop_error ),
       .signal         ( rxd_stop_error      )
 
 
);
 
 
 
 
io_probe_in
#(.MESG("uart_host parity error"))
rxd_parity_error_prb
(
       .clk            ( clk                   ),
       .expected_value ( exp_rxd_parity_error  ),
       .mask           ( mask_rxd_parity_error ),
       .signal         ( rxd_parity_error      )
 
 
);
 
 
 
always@(posedge clk)
if(reset)
  begin
  parity_enable        <= 1'b0;
  txd_data_in          <= 8'h00;
  txd_parity           <= 1'b0;
  txd_force_parity     <= 1'b0;
  txd_load             <= 1'b0;
  txd_break            <= 1'b0;
  rxd_parity           <= 1'b0;
  rxd_force_parity     <= 1'b0;
  rxd_data_avail_stb   <= 1'b0;
  exp_rxd_stop_error   <= 1'b0;
  exp_rxd_parity_error <= 1'b0;
  exp_rxd_data_out     <= 8'h00;
 
  mask_rxd_stop_error   <= 1'b0;
  mask_rxd_parity_error <= 1'b0;
  mask_rxd_data_out     <= 8'h00;
 
 
 end
 
 
 
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2			`/**********************************************************************/`
3			`/* */`
4			`/* ------- */`
5			`/* / SOC \ */`
6			`/* / GEN \ */`
7			`/* / SIM \ */`
8			`/* ============== */`
9			`/* \| \| */`
10			`/* \|____________\| */`
11			`/* */`
12			`/* uart host model for simulations */`
13			`/* */`
14			`/* */`
15			`/* Author(s): */`
16			`/* - John Eaton, jt_eaton@opencores.org */`
17			`/* */`
18			`/**********************************************************************/`
19			`/* */`
20			`/* Copyright (C) <2010> <Ouabache Design Works> */`
21			`/* */`
22			`/* This source file may be used and distributed without */`
23			`/* restriction provided that this copyright statement is not */`
24			`/* removed from the file and that any derivative work contains */`
25			`/* the original copyright notice and the associated disclaimer. */`
26			`/* */`
27			`/* This source file is free software; you can redistribute it */`
28			`/* and/or modify it under the terms of the GNU Lesser General */`
29			`/* Public License as published by the Free Software Foundation; */`
30			`/* either version 2.1 of the License, or (at your option) any */`
31			`/* later version. */`
32			`/* */`
33			`/* This source is distributed in the hope that it will be */`
34			`/* useful, but WITHOUT ANY WARRANTY; without even the implied */`
35			`/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */`
36			`/* PURPOSE. See the GNU Lesser General Public License for more */`
37			`/* details. */`
38			`/* */`
39			`/* You should have received a copy of the GNU Lesser General */`
40			`/* Public License along with this source; if not, download it */`
41			`/* from http://www.opencores.org/lgpl.shtml */`
42			`/* */`
43			`/**********************************************************************/`
44
45
46
47			`module uart_host_def (`
48			`input wire clk,`
49			`input wire reset,`
50			`output reg parity_enable,`
51			`output reg txd_parity,`
52			`output reg txd_force_parity,`
53			`output reg [7:0] txd_data_in,`
54			`input wire txd_buffer_empty,`
55			`output reg txd_load,`
56			`output reg txd_break,`
57			`output reg rxd_parity,`
58			`output reg rxd_force_parity,`
59			`output reg rxd_data_avail_stb,`
60	134	jt_eaton	`input wire [7:0] rxd_data_out,`
61	131	jt_eaton	`input wire rxd_data_avail,`
62	134	jt_eaton	`input wire rxd_stop_error,`
63			`input wire rxd_parity_error`
64	131	jt_eaton	`);`
65
66			`reg exp_rxd_stop_error;`
67			`reg exp_rxd_parity_error;`
68			`reg [7:0] exp_rxd_data_out;`
69
70			`reg mask_rxd_stop_error;`
71			`reg mask_rxd_parity_error;`
72			`reg [7:0] mask_rxd_data_out;`
73
74
75
76	134	jt_eaton	`io_probe_in`
77	131	jt_eaton	`#(.MESG("uart_host receive error"),`
78			`.WIDTH(8))`
79			`rxd_data_out_prb`
80			`(`
81			`.clk ( clk ),`
82			`.expected_value ( exp_rxd_data_out ),`
83			`.mask ( mask_rxd_data_out ),`
84			`.signal ( rxd_data_out )`
85
86
87			`);`
88
89
90
91
92
93
94	134	jt_eaton	`io_probe_in`
95	131	jt_eaton	`#(.MESG("uart_host stop error"))`
96			`rxd_stop_error_prb`
97			`(`
98			`.clk ( clk ),`
99			`.expected_value ( exp_rxd_stop_error ),`
100			`.mask ( mask_rxd_stop_error ),`
101			`.signal ( rxd_stop_error )`
102
103
104			`);`
105
106
107
108
109	134	jt_eaton	`io_probe_in`
110	131	jt_eaton	`#(.MESG("uart_host parity error"))`
111			`rxd_parity_error_prb`
112			`(`
113	134	jt_eaton	`.clk ( clk ),`
114	131	jt_eaton	`.expected_value ( exp_rxd_parity_error ),`
115			`.mask ( mask_rxd_parity_error ),`
116			`.signal ( rxd_parity_error )`
117
118
119			`);`
120
121	134	jt_eaton
122	131	jt_eaton
123	134	jt_eaton	`always@(posedge clk)`
124			`if(reset)`
125			`begin`
126			`parity_enable <= 1'b0;`
127			`txd_data_in <= 8'h00;`
128			`txd_parity <= 1'b0;`
129			`txd_force_parity <= 1'b0;`
130			`txd_load <= 1'b0;`
131			`txd_break <= 1'b0;`
132			`rxd_parity <= 1'b0;`
133			`rxd_force_parity <= 1'b0;`
134			`rxd_data_avail_stb <= 1'b0;`
135			`exp_rxd_stop_error <= 1'b0;`
136			`exp_rxd_parity_error <= 1'b0;`
137			`exp_rxd_data_out <= 8'h00;`
138
139			`mask_rxd_stop_error <= 1'b0;`
140			`mask_rxd_parity_error <= 1'b0;`
141			`mask_rxd_data_out <= 8'h00;`
142
143
144			`end`
145
146
147	131	jt_eaton
148	134	jt_eaton
149	131	jt_eaton
150
151
152
153			`endmodule`
154

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [verilog/] [top.syn] - Blame information for rev 134