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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [xml/] [uart_host_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
uart_host
def
 

 
 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      uart_host_def
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      uart_host_def
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
 :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 

  gen_verilogLib_syn
  105.0
  none
 :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 

 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
 
 
 
  
 
             
              Hierarchical
              Hierarchical
              
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
txd_data_in
reg
  out
  70


 
 
rxd_data_out
wire
  in
  70


 
 
 
 
parity_enable
reg
out

 
txd_parity
reg
out

 
txd_force_parity
reg
out

 
txd_buffer_empty
wire
in

 
txd_load
reg
out

 
 
txd_break
reg
out

 
 
rxd_parity
reg
out

 
 
rxd_force_parity
reg
out

 
 
rxd_data_avail_stb
reg
out

 
 
 
 
rxd_data_avail
wire
in

 
rxd_stop_error
wire
in

 
rxd_parity_error
wire
in

 
 
 
 

 

 
 
  
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/code
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tasks
        verilogSourcefragment
      
 
 
 
 
 
 
      
        
        ../verilog/sim/uart_host_def
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/code
        verilogSourcefragment
      
 
 
      
        
        ../verilog/syn/uart_host_def
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
  
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [xml/] [uart_host_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Testbench`
39			`uart_host`
40			`def`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44	134	jt_eaton
45
46
47
48
49	135	jt_eaton
50			`gen_verilog_sim`
51			`104.0`
52			`none`
53			`:Simulation:`
54			`tools/verilog/gen_verilog`
55
56
57			`destination`
58			`uart_host_def`
59
60
61
62	134	jt_eaton
63
64	135	jt_eaton
65			`gen_verilog_syn`
66			`104.0`
67			`none`
68			`:Synthesis:`
69			`tools/verilog/gen_verilog`
70
71
72			`destination`
73			`uart_host_def`
74
75
76
77	134	jt_eaton
78
79
80
81	135	jt_eaton
82			`gen_verilogLib_sim`
83			`105.0`
84			`none`
85			`:Simulation:`
86			`tools/verilog/gen_verilogLib`
87
88
89			`dest_dir`
90			`../views`
91
92
93			`view`
94			`sim`
95
96
97
98	131	jt_eaton
99	135	jt_eaton
100			`gen_verilogLib_syn`
101			`105.0`
102			`none`
103			`:Synthesis:`
104			`tools/verilog/gen_verilogLib`
105
106
107			`dest_dir`
108			`../views`
109
110
111			`view`
112			`syn`
113
114
115
116	131	jt_eaton
117	135	jt_eaton
118	131	jt_eaton
119
120
121	135	jt_eaton
122	131	jt_eaton
123	135	jt_eaton
124
125			`Hierarchical`
126
127
128
129	131	jt_eaton
130	134	jt_eaton
131	135	jt_eaton
132	134	jt_eaton
133
134	135	jt_eaton
135
136
137
138
139			`Hierarchical`
140			`Hierarchical`
141
142
143
144
145
146
147			`sim:Simulation:`
148	131	jt_eaton
149	135	jt_eaton	`Verilog`
150
151
152			`fs-sim`
153
154
155	131	jt_eaton
156	135	jt_eaton
157			`syn:Synthesis:`
158	131	jt_eaton
159	135	jt_eaton	`Verilog`
160
161
162			`fs-syn`
163
164
165	131	jt_eaton
166
167
168	135	jt_eaton
169			`doc`
170
171
172			`ipxact:library="Testbench"`
173			`ipxact:name="toolflow"`
174			`ipxact:version="documentation"/>`
175
176			`:Documentation:`
177			`Verilog`
178
179	131	jt_eaton
180	135	jt_eaton
181	131	jt_eaton
182
183	135	jt_eaton
184	131	jt_eaton
185	135	jt_eaton	`clk`
186			`wire`
187			`in`
188
189	131	jt_eaton
190	135	jt_eaton	`reset`
191			`wire`
192			`in`
193
194	131	jt_eaton
195
196	134	jt_eaton
197
198	135	jt_eaton	`txd_data_in`
199			`reg`
200			`out`
201			`70`
202
203
204	134	jt_eaton
205
206	135	jt_eaton	`rxd_data_out`
207			`wire`
208			`in`
209			`70`
210
211
212	134	jt_eaton
213
214
215
216	135	jt_eaton	`parity_enable`
217			`reg`
218			`out`
219
220	131	jt_eaton
221	135	jt_eaton	`txd_parity`
222			`reg`
223			`out`
224
225	131	jt_eaton
226	135	jt_eaton	`txd_force_parity`
227			`reg`
228			`out`
229
230	131	jt_eaton
231	135	jt_eaton	`txd_buffer_empty`
232			`wire`
233			`in`
234
235	131	jt_eaton
236	135	jt_eaton	`txd_load`
237			`reg`
238			`out`
239
240	134	jt_eaton
241
242	135	jt_eaton	`txd_break`
243			`reg`
244			`out`
245
246	134	jt_eaton
247
248	135	jt_eaton	`rxd_parity`
249			`reg`
250			`out`
251
252	134	jt_eaton
253
254	135	jt_eaton	`rxd_force_parity`
255			`reg`
256			`out`
257
258	134	jt_eaton
259
260	135	jt_eaton	`rxd_data_avail_stb`
261			`reg`
262			`out`
263
264	134	jt_eaton
265
266
267
268	135	jt_eaton	`rxd_data_avail`
269			`wire`
270			`in`
271
272	131	jt_eaton
273	135	jt_eaton	`rxd_stop_error`
274			`wire`
275			`in`
276
277	131	jt_eaton
278	135	jt_eaton	`rxd_parity_error`
279			`wire`
280			`in`
281
282	131	jt_eaton
283
284
285
286	135	jt_eaton
287	131	jt_eaton
288	135	jt_eaton
289	131	jt_eaton
290
291	135	jt_eaton
292	131	jt_eaton
293
294	135	jt_eaton
295			`fs-sim`
296	131	jt_eaton
297	135	jt_eaton
298
299			`../verilog/copyright`
300			`verilogSourceinclude`
301
302	131	jt_eaton
303	135	jt_eaton
304
305			`../verilog/code`
306			`verilogSourcefragment`
307
308	134	jt_eaton
309
310	135	jt_eaton
311
312			`../verilog/tasks`
313			`verilogSourcefragment`
314
315	134	jt_eaton
316
317
318
319
320
321	135	jt_eaton
322
323			`../verilog/sim/uart_host_def`
324			`verilogSourcemodule`
325
326	134	jt_eaton
327	135	jt_eaton
328			`dest_dir../views/sim/`
329			`verilogSourcelibraryDir`
330
331	134	jt_eaton
332
333
334
335
336	135	jt_eaton
337	134	jt_eaton
338	135	jt_eaton
339			`fs-syn`
340	134	jt_eaton
341	135	jt_eaton
342
343			`../verilog/copyright`
344			`verilogSourceinclude`
345
346	134	jt_eaton
347	135	jt_eaton
348
349			`../verilog/code`
350			`verilogSourcefragment`
351
352	134	jt_eaton
353
354	135	jt_eaton
355
356			`../verilog/syn/uart_host_def`
357			`verilogSourcemodule`
358
359	134	jt_eaton
360	135	jt_eaton
361			`dest_dir../views/syn/`
362			`verilogSourcelibraryDir`
363
364	134	jt_eaton
365
366	135	jt_eaton
367	134	jt_eaton
368
369
370	135	jt_eaton
371	134	jt_eaton
372
373
374
375
376	135	jt_eaton