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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [xml/] [uart_host_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
uart_host
def  default
 

 
 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_host_def
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_host_def
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
 :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 

  gen_verilogLib_syn
  105.0
  none
 :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 

       
 
             
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="uart_host"
                                   spirit:version="def.design"/>
              
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 

 
clk
wire
in

 
reset
wire
in

 
 
 
 
txd_data_in
reg

  out
  70


 
 
rxd_data_out
wire

  in
  70


 
 
 
 
parity_enable
reg
out

 
txd_parity
reg
out

 
txd_force_parity
reg
out

 
txd_buffer_empty
wire
in

 
txd_load
reg
out

 
 
txd_break
reg
out

 
 
rxd_parity
reg
out

 
 
rxd_force_parity
reg
out

 
 
rxd_data_avail_stb
reg
out

 
 
 
 
rxd_data_avail
wire
in

 
rxd_stop_error
wire
in

 
rxd_parity_error
wire
in

 
 
 
 

 

 
 
  
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/code
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tasks
        verilogSourcefragment
      
 
 
 
 
 
 
      
        
        ../verilog/sim/uart_host_def
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/code
        verilogSourcefragment
      
 
 
      
        
        ../verilog/syn/uart_host_def
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
  
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_host/] [rtl/] [xml/] [uart_host_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`uart_host`
40			`def default`
41
42
43
44	134	jt_eaton
45
46
47
48
49	131	jt_eaton
50	134	jt_eaton	`gen_verilog_sim`
51			`104.0`
52			`none`
53			`:Simulation:`
54			`./tools/verilog/gen_verilog`
55
56
57			`destination`
58			`uart_host_def`
59
60
61
62
63
64
65			`gen_verilog_syn`
66			`104.0`
67			`none`
68			`:Synthesis:`
69			`./tools/verilog/gen_verilog`
70
71
72			`destination`
73			`uart_host_def`
74
75
76
77
78
79
80
81
82	131	jt_eaton	`gen_verilogLib_sim`
83			`105.0`
84			`none`
85			`:Simulation:`
86			`./tools/verilog/gen_verilogLib`
87
88
89			`dest_dir`
90			`../views`
91
92
93			`view`
94			`sim`
95
96
97
98
99
100			`gen_verilogLib_syn`
101			`105.0`
102			`none`
103			`:Synthesis:`
104			`./tools/verilog/gen_verilogLib`
105
106
107			`dest_dir`
108			`../views`
109
110
111			`view`
112			`syn`
113
114
115
116
117
118
119
120
121
122
123
124	134	jt_eaton
125	131	jt_eaton	`Hierarchical`
126
127
128			`spirit:library="Testbench"`
129	134	jt_eaton	`spirit:name="uart_host"`
130	131	jt_eaton	`spirit:version="def.design"/>`
131
132
133	134	jt_eaton
134
135
136	131	jt_eaton
137			`sim:Simulation:`
138
139			`Verilog`
140
141
142			`fs-sim`
143
144
145
146
147			`syn:Synthesis:`
148
149			`Verilog`
150
151
152			`fs-syn`
153
154
155
156
157
158
159			`doc`
160
161
162			`spirit:library="Testbench"`
163			`spirit:name="toolflow"`
164			`spirit:version="documentation"/>`
165
166			`:Documentation:`
167			`Verilog`
168
169
170
171
172
173
174
175			`clk`
176			`wire`
177			`in`
178
179
180			`reset`
181			`wire`
182			`in`
183
184
185
186	134	jt_eaton
187
188			`txd_data_in`
189			`reg`
190
191			`out`
192			`70`
193
194
195
196
197			`rxd_data_out`
198			`wire`
199
200			`in`
201			`70`
202
203
204
205
206
207
208	131	jt_eaton	`parity_enable`
209			`reg`
210			`out`
211
212
213			`txd_parity`
214			`reg`
215			`out`
216
217
218			`txd_force_parity`
219			`reg`
220			`out`
221
222
223			`txd_buffer_empty`
224			`wire`
225			`in`
226
227
228	134	jt_eaton	`txd_load`
229			`reg`
230			`out`
231
232
233
234			`txd_break`
235			`reg`
236			`out`
237
238
239
240			`rxd_parity`
241			`reg`
242			`out`
243
244
245
246			`rxd_force_parity`
247			`reg`
248			`out`
249
250
251
252			`rxd_data_avail_stb`
253			`reg`
254			`out`
255
256
257
258
259
260	131	jt_eaton	`rxd_data_avail`
261			`wire`
262			`in`
263
264
265			`rxd_stop_error`
266			`wire`
267			`in`
268
269
270			`rxd_parity_error`
271			`wire`
272			`in`
273
274
275
276
277
278
279
280
281
282
283	134	jt_eaton
284	131	jt_eaton
285
286	134	jt_eaton
287			`fs-sim`
288	131	jt_eaton
289	134	jt_eaton
290
291			`../verilog/copyright`
292			`verilogSourceinclude`
293
294	131	jt_eaton
295	134	jt_eaton
296
297			`../verilog/code`
298			`verilogSourcefragment`
299
300
301
302
303
304			`../verilog/tasks`
305			`verilogSourcefragment`
306
307
308
309
310
311
312
313
314
315			`../verilog/sim/uart_host_def`
316			`verilogSourcemodule`
317
318
319
320			`dest_dir../views/sim/`
321			`verilogSourcelibraryDir`
322
323
324
325
326
327
328
329
330
331			`fs-syn`
332
333
334
335			`../verilog/copyright`
336			`verilogSourceinclude`
337
338
339
340
341			`../verilog/code`
342			`verilogSourcefragment`
343
344
345
346
347
348			`../verilog/syn/uart_host_def`
349			`verilogSourcemodule`
350
351
352
353			`dest_dir../views/syn/`
354			`verilogSourcelibraryDir`
355
356
357
358
359
360
361
362
363
364
365
366
367
368	131	jt_eaton