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jt_eaton |
/**********************************************************************/
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/* */
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/* ------- */
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/* / SOC \ */
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/* / GEN \ */
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/* / LIB \ */
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/* ============== */
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/* | | */
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/* |____________| */
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/* */
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/* Generic model for a serial asynchronous transmitter */
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/* */
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/* Author(s): */
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/* - John Eaton, jt_eaton@opencores.org */
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/* */
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/**********************************************************************/
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/* */
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/* Copyright (C) <2010> */
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/* */
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/* This source file may be used and distributed without */
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/* restriction provided that this copyright statement is not */
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/* removed from the file and that any derivative work contains */
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/* the original copyright notice and the associated disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it */
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/* and/or modify it under the terms of the GNU Lesser General */
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/* Public License as published by the Free Software Foundation; */
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/* either version 2.1 of the License, or (at your option) any */
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/* later version. */
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/* */
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/* This source is distributed in the hope that it will be */
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/* useful, but WITHOUT ANY WARRANTY; without even the implied */
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/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
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/* PURPOSE. See the GNU Lesser General Public License for more */
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/* details. */
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/* */
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/* You should have received a copy of the GNU Lesser General */
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/* Public License along with this source; if not, download it */
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/* from http://www.opencores.org/lgpl.shtml */
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/* */
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/**********************************************************************/
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module
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uart_model_serial_xmit
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#(parameter WIDTH=8, // Number of data bits
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parameter SIZE=4 // binary size of shift_cnt, must be able to hold WIDTH + 4 states
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)
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(
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input wire clk,
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input wire reset,
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input wire edge_enable, // one pulse per bit time for data rate timing
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input wire parity_enable, // 0 = no parity bit sent, 1= parity bit sent
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input wire two_stop_enable, // 0 = 1 stop bit, 1 = 2 stop bits
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input wire [1:0] parity_type, // 00= odd,01=even,10=force a 0,11= force a 1
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input wire load, // start transmiting data
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input wire start_value, // value out at start bit time
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input wire stop_value, // value out for stop bit also used for break
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input wire [WIDTH-1:0] data, // data byte
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output reg buffer_empty, // ready for next byte
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output reg ser_out // to pad_ring
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);
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reg [SIZE-1:0] shift_cnt;
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reg [WIDTH-1:0] shift_buffer;
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reg parity_calc;
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reg delayed_edge_enable;
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//
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// shift_cnt controls the serial bit out
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//
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// 0 Start bit
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// 1-> WIDTH Data bit lsb first
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// WIDTH+1 Parity bit if enabled
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// 2^SIZE-2 Second stop bit if enabled
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// 2^SIZE-1 Last stop bit and idle
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always@(posedge clk)
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if(reset || buffer_empty) shift_cnt <= {SIZE{1'b1}};
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else
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if(!edge_enable) shift_cnt <= shift_cnt;
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else
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if(( shift_cnt == {SIZE{1'b1}} ) && ! buffer_empty ) shift_cnt <= {SIZE{1'b0}};
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else
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if ( shift_cnt == WIDTH)
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case({two_stop_enable,parity_enable})
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(2'b00): shift_cnt <= {SIZE{1'b1}};
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(2'b01): shift_cnt <= shift_cnt + 1'b1;
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(2'b10): shift_cnt <= {SIZE{1'b1}} - 1'b1;
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(2'b11): shift_cnt <= shift_cnt + 1'b1;
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endcase // case ({two_stop_enable,parity_enable})
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else
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if ( shift_cnt == (WIDTH+1))
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case( two_stop_enable)
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(1'b0): shift_cnt <= {SIZE{1'b1}};
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(1'b1): shift_cnt <= {SIZE{1'b1}} - 1'b1;
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endcase
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else shift_cnt <= shift_cnt + 1'b1;
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//
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//
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// Clear buffer_empty upon load pulse
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// set it back at the start of the final stop pulse
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// if load happens BEFORE the next edge_enable then data transfer will have no pauses
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// logic ensures that having load happen on a edge_enable will work
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//
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always@(posedge clk)
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if(reset) delayed_edge_enable <= 1'b0;
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else delayed_edge_enable <= edge_enable && ! load;
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always@(posedge clk)
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if(reset) buffer_empty <= 1'b1;
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else
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if(load) buffer_empty <= 1'b0;
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else
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if((shift_cnt == {SIZE{1'b1}}) && delayed_edge_enable)
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buffer_empty <= 1'b1;
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else buffer_empty <= buffer_empty;
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//
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//
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// load shift_buffer during start_bit
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// shift down every bit
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//
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//
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always@(posedge clk)
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if(reset) shift_buffer <= {WIDTH{1'b0}};
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else
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if(!edge_enable) shift_buffer <= shift_buffer;
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else
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if(shift_cnt == {SIZE{1'b0}}) shift_buffer <= data;
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else shift_buffer <= {1'b0,shift_buffer[WIDTH-1:1]};
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//
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//
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// calculate parity on the fly
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// seed reg with 0 for odd and 1 for even
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// force reg to 0 or 1 if needed
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//
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always@(posedge clk)
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if(reset) parity_calc <= 1'b0;
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else
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if(!edge_enable) parity_calc <= parity_calc;
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else
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if(parity_type[1] || (shift_cnt == {SIZE{1'b0}})) parity_calc <= parity_type[0];
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else parity_calc <= parity_calc ^ shift_buffer[0];
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// send start_bit,data,parity and stop based on shift_cnt
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always@(posedge clk)
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if(reset) ser_out <= stop_value;
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else
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if( shift_cnt == {SIZE{1'b0}} ) ser_out <= start_value;
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else
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if( shift_cnt == {SIZE{1'b1}} ) ser_out <= stop_value;
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else
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if( shift_cnt == ({SIZE{1'b1}}+1'b1) ) ser_out <= stop_value;
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else
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if( shift_cnt == (WIDTH+1) ) ser_out <= parity_calc;
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else ser_out <= shift_buffer[0];
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endmodule
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