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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [verilog/] [top.tasks] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
 
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task next;
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  input [31:0] num;
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  repeat (num)       @ (posedge clk);
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endtask
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task wait_tx;
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begin
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  while(!txd_buffer_empty) next(1);
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end
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endtask // wait_tx
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task send_byte;
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  input [7:0] byte_out;
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begin
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  while(!txd_buffer_empty) next(1);
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  $display("%t %m        %2h",$realtime ,byte_out  );
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  txd_data_in  = byte_out;
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  next(1);
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  txd_load   = 1'b1;
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  next(1);
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  txd_load   = 1'b0;
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  next(1);
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end
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endtask // send_byte
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task rcv_byte;
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  input [7:0] byte_in;
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   begin
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   exp_rx_shift_buffer <= byte_in;
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   while(!rx_frame_rdy)  next(1);
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   $display("%t %m check   %h   %h ",$realtime,rx_shift_buffer,byte_in);
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   mask_rx_frame_err    <= 1'b1;
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   mask_rx_parity_err   <= 1'b1;
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   mask_rx_shift_buffer <= 8'hff;
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   next(1);
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   mask_rx_frame_err    <= 1'b0;
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   mask_rx_parity_err   <= 1'b0;
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   mask_rx_shift_buffer <= 8'h00;
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end
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endtask
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