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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [xml/] [uart_model_def.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
uart_model
def.design
 
 

 

 
 
 
 
exp_rx_shift_buffer
reg

70

 
 
mask_rx_shift_buffer
reg

70

 
 
 
exp_rx_parity_err
reg

 
 
mask_rx_parity_err
reg

 
 

 

 
 
 
 

 
 
    
      clk
      
      
      
    
 
 
 
    
      exp_rx_shift_buffer
      
      
    
 
 
    
      exp_rx_parity_err
      
      
    
 
 
    
      drv_rx_shift_buffer
      
      
    
 
 
    
      drv_rx_parity_err
      
      
    
 
 
 
    
      mask_rx_shift_buffer
      
      
    
 
 
    
      mask_rx_parity_err
      
      
    
 
 
 
 
 
    
      prb_rx_shift_buffer
      
      
    
 
 
    
      prb_rx_parity_err
      
      
    
 
 
 

 
 
 

 
 
 
 
 

rx_shift_buffer_prb 
 
 8
 "uart data receive  Error"


 
 

rx_parity_err_prb 
 
 1
 "uart parity Error"


 
 
 
 
 

 
 


Line No.	Rev	Author	Line
1	133	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	133	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	133	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Testbench`
39			`uart_model`
40			`def.design`
41	133	jt_eaton
42
43	135	jt_eaton
44	133	jt_eaton
45
46
47
48
49
50	135	jt_eaton	`exp_rx_shift_buffer`
51			`reg`
52
53			`70`
54	133	jt_eaton
55
56
57	135	jt_eaton	`mask_rx_shift_buffer`
58			`reg`
59
60			`70`
61	133	jt_eaton
62
63
64
65	135	jt_eaton	`exp_rx_parity_err`
66			`reg`
67	133	jt_eaton
68
69
70	135	jt_eaton	`mask_rx_parity_err`
71			`reg`
72	133	jt_eaton
73
74
75
76
77	135	jt_eaton
78	133	jt_eaton
79
80
81
82	135	jt_eaton
83	133	jt_eaton
84
85	135	jt_eaton
86			`clk`
87
88
89
90
91	133	jt_eaton
92
93
94	135	jt_eaton
95			`exp_rx_shift_buffer`
96
97
98
99	133	jt_eaton
100
101	135	jt_eaton
102			`exp_rx_parity_err`
103
104
105
106	133	jt_eaton
107
108	135	jt_eaton
109			`drv_rx_shift_buffer`
110
111
112
113	133	jt_eaton
114
115	135	jt_eaton
116			`drv_rx_parity_err`
117
118
119
120	133	jt_eaton
121
122
123	135	jt_eaton
124			`mask_rx_shift_buffer`
125
126
127
128	133	jt_eaton
129
130	135	jt_eaton
131			`mask_rx_parity_err`
132
133
134
135	133	jt_eaton
136
137
138
139
140	135	jt_eaton
141			`prb_rx_shift_buffer`
142
143
144
145	133	jt_eaton
146
147	135	jt_eaton
148			`prb_rx_parity_err`
149
150
151
152	133	jt_eaton
153
154
155	135	jt_eaton
156	133	jt_eaton
157
158
159	135	jt_eaton
160	133	jt_eaton
161
162
163
164
165	135	jt_eaton
166			`rx_shift_buffer_prb`
167
168			`8`
169			`"uart data receive Error"`
170
171
172	133	jt_eaton
173
174	135	jt_eaton
175			`rx_parity_err_prb`
176
177			`1`
178			`"uart parity Error"`
179
180
181	133	jt_eaton
182
183
184
185
186	135	jt_eaton
187	133	jt_eaton
188
189	135	jt_eaton

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [xml/] [uart_model_def.design.xml] - Blame information for rev 135