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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [xml/] [uart_model_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
uart_model
def  default
 
 
 
 
 
 
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.tasks
        verilogSourcefragment
      
 
 
      
        
        ../verilog/serial_rcvr
        verilogSourcemodule
      
 
      
        
        ../verilog/serial_xmit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/divider
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
 
    
 
 
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
      
        
        ../verilog/serial_rcvr
        verilogSourcemodule
      
 
      
        
        ../verilog/serial_xmit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/divider
        verilogSourcemodule
      
 
 
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 
  
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="io_probe"
                                   spirit:version="def.design"/>
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

CLKCNT4'h5
SIZE4

 

 
clk
wire
in

 
reset
wire
in

 
 
txd_in
wire
in

 
rxd_out
wire
out

 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [xml/] [uart_model_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`uart_model`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog_sim`
52			`104.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59			`top.out.sim`
60
61
62			`dest_dir`
63			`../verilog`
64
65
66
67
68
69
70			`gen_verilog_syn`
71			`104.0`
72			`none`
73			`:Synthesis:`
74			`./tools/verilog/gen_verilog`
75
76
77			`destination`
78			`top.out.syn`
79
80
81			`dest_dir`
82			`../verilog`
83
84
85
86
87
88
89
90			`gen_verilogLib_sim`
91			`105.0`
92			`none`
93			`:Simulation:`
94			`./tools/verilog/gen_verilogLib`
95
96
97			`dest_dir`
98			`../views`
99
100
101			`view`
102			`sim`
103
104
105
106
107
108			`gen_verilogLib_syn`
109			`105.0`
110			`none`
111			`:Synthesis:`
112			`./tools/verilog/gen_verilogLib`
113
114
115			`dest_dir`
116			`../views`
117
118
119			`view`
120			`syn`
121
122
123
124
125
126
127
128
129
130
131
132			`fs-sim`
133
134
135
136			`../verilog/copyright.v`
137			`verilogSourceinclude`
138
139
140
141
142			`../verilog/sim/top.out.sim`
143			`verilogSourcemodule`
144
145
146
147
148
149			`../verilog/top.rtl`
150			`verilogSourcefragment`
151
152
153
154
155
156			`../verilog/top.tasks`
157			`verilogSourcefragment`
158
159
160
161
162
163			`../verilog/serial_rcvr`
164			`verilogSourcemodule`
165
166
167
168
169			`../verilog/serial_xmit`
170			`verilogSourcemodule`
171
172
173
174
175
176			`../verilog/divider`
177			`verilogSourcemodule`
178
179
180
181			`dest_dir../views/sim/`
182			`verilogSourcelibraryDir`
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199			`fs-syn`
200
201
202
203			`../verilog/copyright.v`
204			`verilogSourceinclude`
205
206
207
208
209			`../verilog/syn/top.out.syn`
210			`verilogSourcemodule`
211
212
213
214
215
216			`../verilog/top.rtl`
217			`verilogSourcefragment`
218
219
220
221
222
223			`../verilog/serial_rcvr`
224			`verilogSourcemodule`
225
226
227
228
229			`../verilog/serial_xmit`
230			`verilogSourcemodule`
231
232
233
234
235
236			`../verilog/divider`
237			`verilogSourcemodule`
238
239
240
241
242
243
244			`dest_dir../views/syn/`
245			`verilogSourcelibraryDir`
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264			`Hierarchical`
265
266
267			`spirit:library="Testbench"`
268			`spirit:name="io_probe"`
269			`spirit:version="def.design"/>`
270
271
272
273			`sim:Simulation:`
274
275			`Verilog`
276
277
278			`fs-sim`
279
280
281
282
283
284			`syn:Synthesis:`
285
286			`Verilog`
287
288
289			`fs-syn`
290
291
292
293
294
295			`doc`
296
297
298			`spirit:library="Testbench"`
299			`spirit:name="toolflow"`
300			`spirit:version="documentation"/>`
301
302			`:Documentation:`
303			`Verilog`
304
305
306
307
308
309
310
311			`CLKCNT4'h5`
312			`SIZE4`
313
314
315
316
317			`clk`
318			`wire`
319			`in`
320
321
322			`reset`
323			`wire`
324			`in`
325
326
327
328			`txd_in`
329			`wire`
330			`in`
331
332
333			`rxd_out`
334			`wire`
335			`out`
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357