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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [xml/] [uart_model_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
uart_model
def  default
 
 
 
 
 
 
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_model_def
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      uart_model_def
    
  

 
 

 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="uart_model"
                                   spirit:version="def.design"/>
              
 
 
             
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

CLKCNT4'h5
SIZE4

 

 
clk
wire
in

 
reset
wire
in

 
 
txd_in
wire
in

 
rxd_out
wire
out

 

 

 
 
 
 
 
 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
      
        
        ../verilog/top.tasks
        verilogSourcefragment
      
 
 
 
      
        
        ../verilog/sim/uart_model_def
        verilogSourcemodule
      
 
 
 
      
        
        ../verilog/serial_rcvr
        verilogSourcemodule
      
 
      
        
        ../verilog/serial_xmit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/divider
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
 
    
 
 
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
      
        
        ../verilog/serial_rcvr
        verilogSourcemodule
      
 
 
 
      
        
        ../verilog/syn/uart_model_def
        verilogSourcemodule
      
 
 
 
      
        
        ../verilog/serial_xmit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/divider
        verilogSourcemodule
      
 
 
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [uart_model/] [rtl/] [xml/] [uart_model_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`uart_model`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog_sim`
52			`104.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59	134	jt_eaton	`uart_model_def`
60	131	jt_eaton
61
62
63
64
65
66			`gen_verilog_syn`
67			`104.0`
68			`none`
69			`:Synthesis:`
70			`./tools/verilog/gen_verilog`
71
72
73			`destination`
74	134	jt_eaton	`uart_model_def`
75	131	jt_eaton
76
77
78
79
80	134	jt_eaton
81	131	jt_eaton
82
83
84
85	134	jt_eaton
86
87	131	jt_eaton
88	134	jt_eaton
89			`Hierarchical`
90
91
92			`spirit:library="Testbench"`
93			`spirit:name="uart_model"`
94			`spirit:version="def.design"/>`
95
96	131	jt_eaton
97	134	jt_eaton
98
99			`verilog`
100
101
102			`spirit:library="Testbench"`
103			`spirit:name="toolflow"`
104			`spirit:version="verilog"/>`
105
106
107
108
109
110
111
112			`sim:Simulation:`
113
114			`Verilog`
115
116
117			`fs-sim`
118
119
120
121
122
123			`syn:Synthesis:`
124
125			`Verilog`
126
127
128			`fs-syn`
129
130
131
132
133
134			`doc`
135
136
137			`spirit:library="Testbench"`
138			`spirit:name="toolflow"`
139			`spirit:version="documentation"/>`
140
141			`:Documentation:`
142			`Verilog`
143
144
145
146
147
148
149
150			`CLKCNT4'h5`
151			`SIZE4`
152
153
154
155
156			`clk`
157			`wire`
158			`in`
159
160
161			`reset`
162			`wire`
163			`in`
164
165
166
167			`txd_in`
168			`wire`
169			`in`
170
171
172			`rxd_out`
173			`wire`
174			`out`
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189	131	jt_eaton
190
191
192			`fs-sim`
193
194
195
196	134	jt_eaton	`../verilog/copyright`
197	131	jt_eaton	`verilogSourceinclude`
198
199
200
201
202	134	jt_eaton	`../verilog/top.rtl`
203			`verilogSourcefragment`
204	131	jt_eaton
205
206
207
208	134	jt_eaton	`../verilog/top.tasks`
209	131	jt_eaton	`verilogSourcefragment`
210
211
212
213	134	jt_eaton
214	131	jt_eaton
215
216	134	jt_eaton	`../verilog/sim/uart_model_def`
217			`verilogSourcemodule`
218	131	jt_eaton
219
220
221	134	jt_eaton
222	131	jt_eaton
223
224			`../verilog/serial_rcvr`
225			`verilogSourcemodule`
226
227
228
229
230			`../verilog/serial_xmit`
231			`verilogSourcemodule`
232
233
234
235
236
237			`../verilog/divider`
238			`verilogSourcemodule`
239
240
241
242			`dest_dir../views/sim/`
243			`verilogSourcelibraryDir`
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260			`fs-syn`
261
262
263
264	134	jt_eaton	`../verilog/copyright`
265	131	jt_eaton	`verilogSourceinclude`
266
267
268	134	jt_eaton
269	131	jt_eaton
270
271	134	jt_eaton	`../verilog/top.rtl`
272			`verilogSourcefragment`
273	131	jt_eaton
274
275
276
277
278	134	jt_eaton	`../verilog/serial_rcvr`
279			`verilogSourcemodule`
280	131	jt_eaton
281
282
283	134	jt_eaton
284	131	jt_eaton
285
286	134	jt_eaton	`../verilog/syn/uart_model_def`
287	131	jt_eaton	`verilogSourcemodule`
288
289
290	134	jt_eaton
291
292	131	jt_eaton
293
294			`../verilog/serial_xmit`
295			`verilogSourcemodule`
296
297
298
299
300
301			`../verilog/divider`
302			`verilogSourcemodule`
303
304
305
306
307
308
309			`dest_dir../views/syn/`
310			`verilogSourcelibraryDir`
311
312
313
314
315
316
317
318
319
320
321
322
323
324
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