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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [verilog/] [top.rtl] - Blame information for rev 134

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assign prb_device_rx_data = 8'h00;
 
assign  prb_device_rx_parity = 1'b0;
 
always@(posedge clk)
  if(reset)
   mask_device_rx_parity <= 1'b0;
  else
   mask_device_rx_parity <= 1'b0;
 
always@(posedge clk)
  if(reset)
   mask_device_rx_data <= 8'b0;
  else
   mask_device_rx_data <= 8'b0;
 
 
 
reg [23:0] red_h_cnt;
reg [23:0] green_h_cnt;
reg [23:0] blue_h_cnt;
 
 
reg [23:0] red_h_lat;
reg [23:0] green_h_lat;
reg [23:0] blue_h_lat;
 
 
reg [47:0] v_cnt;
reg [47:0] v_lat;
 
reg hsync;
reg vsync;
 
 
 
always@(posedge clk)
if(reset)             hsync <= 1'b0;
else                  hsync <= !hsync_n;
 
 
always@(posedge clk)
if(reset)             vsync <= 1'b0;
else                  vsync <= !vsync_n;
 
 
 
 
always@(posedge clk)
if(reset || (hsync))               red_h_cnt <= 24'h0;
else                               red_h_cnt <= red_h_cnt + red;
 
always@(posedge clk)
if   (reset)                       red_h_lat <= 24'h0;
else if(!hsync_n &&(!hsync))       red_h_lat <= red_h_cnt;
else                               red_h_lat <= red_h_lat;
 
always@(posedge clk)
if(reset || (hsync))               green_h_cnt <= 24'h0;
else                               green_h_cnt <= green_h_cnt + green;
 
always@(posedge clk)
if   (reset)                       green_h_lat <= 24'h0;
else if(!hsync_n &&(!hsync))       green_h_lat <= green_h_cnt;
else                               green_h_lat <= green_h_lat;
 
always@(posedge clk)
if(reset || (hsync))               blue_h_cnt <= 24'h0;
else                               blue_h_cnt <= blue_h_cnt + blue;
 
always@(posedge clk)
if   (reset)                       blue_h_lat <= 24'h0;
else if(!hsync_n &&(!hsync))       blue_h_lat <= blue_h_lat;
else                               blue_h_lat <= blue_h_cnt;
 
 
 
always@(posedge clk)
if   (reset)                       v_cnt      <= 48'h0;
else if(!hsync_n &&(!hsync))       v_cnt      <= red_h_cnt + green_h_cnt + blue_h_cnt + v_cnt;
else                               v_cnt      <= v_cnt;
 
 
 
 
 
always@(posedge clk)
if   (reset)                       v_lat <= 48'h0;
else if(!vsync_n &&(vsync))        v_lat <= v_cnt;
else                               v_lat <= v_lat;
 
 
 
 
 
 
 
 
/*
io_probe_in
#(.MESG   ("vga data receive error"),
  .WIDTH  (8)
  )
rx_shift_buffer_prb
(
  .clk           ( clk ),
  .expected_value( exp_rx_shift_buffer),
  .mask          ( mask_rx_shift_buffer),
  .signal        ( prb_rx_shift_buffer)
);
 
 
io_probe_in
#(.MESG   ("vga parity error"))
rx_parity_err_prb
(
  .clk           ( clk ),
  .expected_value( exp_rx_parity_err),
  .mask          ( mask_rx_parity_err),
  .signal        ( prb_rx_parity_err)
);
 
*/
 
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3	134	jt_eaton	`assign prb_device_rx_data = 8'h00;`
4	131	jt_eaton
5	134	jt_eaton	`assign prb_device_rx_parity = 1'b0;`
6	131	jt_eaton
7	134	jt_eaton	`always@(posedge clk)`
8			`if(reset)`
9			`mask_device_rx_parity <= 1'b0;`
10			`else`
11			`mask_device_rx_parity <= 1'b0;`
12	131	jt_eaton
13	134	jt_eaton	`always@(posedge clk)`
14			`if(reset)`
15			`mask_device_rx_data <= 8'b0;`
16			`else`
17			`mask_device_rx_data <= 8'b0;`
18
19
20
21	131	jt_eaton	`reg [23:0] red_h_cnt;`
22			`reg [23:0] green_h_cnt;`
23			`reg [23:0] blue_h_cnt;`
24
25
26			`reg [23:0] red_h_lat;`
27			`reg [23:0] green_h_lat;`
28			`reg [23:0] blue_h_lat;`
29
30
31			`reg [47:0] v_cnt;`
32			`reg [47:0] v_lat;`
33
34			`reg hsync;`
35			`reg vsync;`
36
37
38
39			`always@(posedge clk)`
40			`if(reset) hsync <= 1'b0;`
41			`else hsync <= !hsync_n;`
42
43
44			`always@(posedge clk)`
45			`if(reset) vsync <= 1'b0;`
46			`else vsync <= !vsync_n;`
47
48
49
50
51			`always@(posedge clk)`
52			`if(reset \|\| (hsync)) red_h_cnt <= 24'h0;`
53			`else red_h_cnt <= red_h_cnt + red;`
54
55			`always@(posedge clk)`
56			`if (reset) red_h_lat <= 24'h0;`
57			`else if(!hsync_n &&(!hsync)) red_h_lat <= red_h_cnt;`
58			`else red_h_lat <= red_h_lat;`
59
60			`always@(posedge clk)`
61			`if(reset \|\| (hsync)) green_h_cnt <= 24'h0;`
62			`else green_h_cnt <= green_h_cnt + green;`
63
64			`always@(posedge clk)`
65			`if (reset) green_h_lat <= 24'h0;`
66			`else if(!hsync_n &&(!hsync)) green_h_lat <= green_h_cnt;`
67			`else green_h_lat <= green_h_lat;`
68
69			`always@(posedge clk)`
70			`if(reset \|\| (hsync)) blue_h_cnt <= 24'h0;`
71			`else blue_h_cnt <= blue_h_cnt + blue;`
72
73			`always@(posedge clk)`
74			`if (reset) blue_h_lat <= 24'h0;`
75			`else if(!hsync_n &&(!hsync)) blue_h_lat <= blue_h_lat;`
76			`else blue_h_lat <= blue_h_cnt;`
77
78
79
80			`always@(posedge clk)`
81			`if (reset) v_cnt <= 48'h0;`
82			`else if(!hsync_n &&(!hsync)) v_cnt <= red_h_cnt + green_h_cnt + blue_h_cnt + v_cnt;`
83			`else v_cnt <= v_cnt;`
84
85
86
87
88
89			`always@(posedge clk)`
90			`if (reset) v_lat <= 48'h0;`
91			`else if(!vsync_n &&(vsync)) v_lat <= v_cnt;`
92			`else v_lat <= v_lat;`
93
94
95
96
97
98
99
100
101			`/*`
102	134	jt_eaton	`io_probe_in`
103	131	jt_eaton	`#(.MESG ("vga data receive error"),`
104			`.WIDTH (8)`
105			`)`
106			`rx_shift_buffer_prb`
107			`(`
108			`.clk ( clk ),`
109			`.expected_value( exp_rx_shift_buffer),`
110			`.mask ( mask_rx_shift_buffer),`
111			`.signal ( prb_rx_shift_buffer)`
112			`);`
113
114
115	134	jt_eaton	`io_probe_in`
116	131	jt_eaton	`#(.MESG ("vga parity error"))`
117			`rx_parity_err_prb`
118			`(`
119			`.clk ( clk ),`
120			`.expected_value( exp_rx_parity_err),`
121			`.mask ( mask_rx_parity_err),`
122			`.signal ( prb_rx_parity_err)`
123			`);`
124
125			`*/`
126
127
128
129
130
131
132
133
134
135
136

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [verilog/] [top.rtl] - Blame information for rev 134