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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [xml/] [vga_model_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
vga_model
def  default
 
 
 
 
 
 
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      vga_model_def
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      vga_model_def
    
  

 
 
 
 
 

 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="Testbench"
                                   spirit:name="vga_model"
                                   spirit:version="def.design"/>
              
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 
 

 
clk
wire
in

 
reset
wire
in

 
 
vsync_n
wire
in

 
hsync_n
wire
in

 
 
red
wire
in20

 
 
green
wire
in20

 
 
blue
wire
in10

 
 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/vga_model_def
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
 
    
 
 
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/vga_model_def
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
 
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [vga_model/] [rtl/] [xml/] [vga_model_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`vga_model`
40			`def default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog_sim`
52			`104.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59	134	jt_eaton	`vga_model_def`
60	131	jt_eaton
61
62
63
64
65
66			`gen_verilog_syn`
67			`104.0`
68			`none`
69			`:Synthesis:`
70			`./tools/verilog/gen_verilog`
71
72
73			`destination`
74	134	jt_eaton	`vga_model_def`
75	131	jt_eaton
76
77
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88	134	jt_eaton
89
90	131	jt_eaton
91	134	jt_eaton
92			`Hierarchical`
93
94
95			`spirit:library="Testbench"`
96			`spirit:name="vga_model"`
97			`spirit:version="def.design"/>`
98
99	131	jt_eaton
100
101
102	134	jt_eaton
103			`verilog`
104
105
106			`spirit:library="Testbench"`
107			`spirit:name="toolflow"`
108			`spirit:version="verilog"/>`
109
110
111	131	jt_eaton
112
113
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119			`sim:Simulation:`
120
121			`Verilog`
122
123
124			`fs-sim`
125
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130			`syn:Synthesis:`
131
132			`Verilog`
133
134
135			`fs-syn`
136
137
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139
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141			`doc`
142
143
144			`spirit:library="Testbench"`
145			`spirit:name="toolflow"`
146			`spirit:version="documentation"/>`
147
148			`:Documentation:`
149			`Verilog`
150
151
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158
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160			`clk`
161			`wire`
162			`in`
163
164
165			`reset`
166			`wire`
167			`in`
168
169
170
171			`vsync_n`
172			`wire`
173			`in`
174
175
176			`hsync_n`
177			`wire`
178			`in`
179
180
181
182			`red`
183			`wire`
184			`in20`
185
186
187
188			`green`
189			`wire`
190			`in20`
191
192
193
194			`blue`
195			`wire`
196			`in10`
197
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218	134	jt_eaton
219	131	jt_eaton
220	134	jt_eaton
221			`fs-sim`
222	131	jt_eaton
223	134	jt_eaton
224
225			`../verilog/copyright`
226			`verilogSourceinclude`
227
228	131	jt_eaton
229	134	jt_eaton
230
231			`../verilog/sim/vga_model_def`
232			`verilogSourcemodule`
233
234	131	jt_eaton
235
236	134	jt_eaton
237
238			`../verilog/top.rtl`
239			`verilogSourcefragment`
240
241
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245			`dest_dir../views/sim/`
246			`verilogSourcelibraryDir`
247
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263			`fs-syn`
264
265
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267			`../verilog/copyright`
268			`verilogSourceinclude`
269
270
271
272
273			`../verilog/syn/vga_model_def`
274			`verilogSourcemodule`
275
276
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279
280			`../verilog/top.rtl`
281			`verilogSourcefragment`
282
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289			`dest_dir../views/syn/`
290			`verilogSourcelibraryDir`
291
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309	131	jt_eaton