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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [src/] [geda/] [sym/] [clock_gen_def.sym] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton 
v 20100214 1
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B 300 0  4000 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 400 1250   5 10 1 1 0 0 1 1
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device=clock_gen_def
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T 400 -300   5 10 0 1 0 0 1 1
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source=clock_gen_def.sch
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T 400 1450 8 10 1 1 0 0 1 1
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refdes=U?
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P 300 200 0 200 4 0 1
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{
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T 400 200 5 10 1 1 0 1 1 1
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pinnumber=BAD
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T 400 200 5 10 0 1 0 1 1 1
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pinseq=1
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}
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P 300 400 0 400 4 0 1
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{
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T 400 400 5 10 1 1 0 1 1 1
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pinnumber=STOP
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T 400 400 5 10 0 1 0 1 1 1
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pinseq=2
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}
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P 300 600 0 600 4 0 1
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{
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T 400 600 5 10 1 1 0 1 1 1
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pinnumber=START
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T 400 600 5 10 0 1 0 1 1 1
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pinseq=3
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}
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P 300 800 0 800 10 1 1
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{
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T 400 800 5 10 1 1 0 1 1 1
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pinnumber=clock__master_clk
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T 400 800 5 10 0 1 0 1 1 1
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pinseq=4
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}
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P 4300 200 4600 200 4 0 1
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{
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T 4200 200 5  10 1 1 0 7 1 1
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pinnumber=FINISH
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T 4200 200 5  10 0 1 0 7 1 1
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pinseq=5
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}
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P 4300 400 4600 400 4 0 1
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{
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T 4200 400 5  10 1 1 0 7 1 1
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pinnumber=FAIL
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T 4200 400 5  10 0 1 0 7 1 1
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pinseq=6
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}
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P 4300 600 4600 600 10 1 1
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{
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T 4200 600 5  10 1 1 0 7 1 1
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pinnumber=reset__master_reset
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T 4200 600 5  10 0 1 0 7 1 1
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pinseq=7
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}

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