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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [sym/] [io_mem_model_def.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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B 300 0  6400 2500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 400 2650   5 10 1 1 0 0 1 1
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device=io_mem_model_def
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T 400 2850 5 10 1 1 0 0 1 1
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refdes=U?
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T 400 3000    0 10 0 1 0 0 1 1
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vendor=opencores.org
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T 400 3000    0 10 0 1 0 0 1 1
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library=Testbench
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T 400 3000    0 10 0 1 0 0 1 1
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component=io_mem_model
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T 400 3000    0 10 0 1 0 0 1 1
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version=def
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P 300 200 0 200 10 1 1
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{
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T 400 200 5 10 1 1 0 1 1 1
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pinnumber=io_mem_req_data_bits_data[127:0]
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T 400 200 5 10 0 1 0 1 1 1
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pinseq=1
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}
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P 300 400 0 400 10 1 1
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{
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T 400 400 5 10 1 1 0 1 1 1
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pinnumber=io_mem_req_cmd_bits_tag[4:0]
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T 400 400 5 10 0 1 0 1 1 1
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pinseq=2
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}
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P 300 600 0 600 10 1 1
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{
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T 400 600 5 10 1 1 0 1 1 1
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pinnumber=io_mem_req_cmd_bits_addr[25:0]
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T 400 600 5 10 0 1 0 1 1 1
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pinseq=3
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}
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P 300 800 0 800 4 0 1
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{
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T 400 800 5 10 1 1 0 1 1 1
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pinnumber=reset
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T 400 800 5 10 0 1 0 1 1 1
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pinseq=4
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}
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P 300 1000 0 1000 4 0 1
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{
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T 400 1000 5 10 1 1 0 1 1 1
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pinnumber=io_mem_req_data_valid
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T 400 1000 5 10 0 1 0 1 1 1
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pinseq=5
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}
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P 300 1200 0 1200 4 0 1
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{
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T 400 1200 5 10 1 1 0 1 1 1
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pinnumber=io_mem_req_cmd_valid
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T 400 1200 5 10 0 1 0 1 1 1
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pinseq=6
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}
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P 300 1400 0 1400 4 0 1
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{
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T 400 1400 5 10 1 1 0 1 1 1
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pinnumber=io_mem_req_cmd_bits_rw
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T 400 1400 5 10 0 1 0 1 1 1
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pinseq=7
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}
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P 300 1600 0 1600 4 0 1
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{
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T 400 1600 5 10 1 1 0 1 1 1
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pinnumber=clk
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T 400 1600 5 10 0 1 0 1 1 1
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pinseq=8
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}
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P 6700 200 7000 200 10 1 1
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{
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T 6600 200 5  10 1 1 0 7 1 1
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pinnumber=io_mem_resp_bits_tag[4:0]
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T 6600 200 5  10 0 1 0 7 1 1
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pinseq=9
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}
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P 6700 400 7000 400 10 1 1
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{
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T 6600 400 5  10 1 1 0 7 1 1
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pinnumber=io_mem_resp_bits_data[127:0]
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T 6600 400 5  10 0 1 0 7 1 1
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pinseq=10
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}
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P 6700 600 7000 600 4 0 1
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{
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T 6600 600 5  10 1 1 0 7 1 1
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pinnumber=io_out_mem_valid
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T 6700 600 5  10 0 1 0 7 1 1
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pinseq=11
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}
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P 6700 800 7000 800 4 0 1
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{
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T 6600 800 5  10 1 1 0 7 1 1
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pinnumber=io_out_mem_ready
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T 6700 800 5  10 0 1 0 7 1 1
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pinseq=12
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}
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P 6700 1000 7000 1000 4 0 1
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{
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T 6600 1000 5  10 1 1 0 7 1 1
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pinnumber=io_mem_resp_valid
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T 6700 1000 5  10 0 1 0 7 1 1
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pinseq=13
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}
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P 6700 1200 7000 1200 4 0 1
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{
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T 6600 1200 5  10 1 1 0 7 1 1
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pinnumber=io_mem_resp_ready
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T 6700 1200 5  10 0 1 0 7 1 1
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pinseq=14
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}
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P 6700 1400 7000 1400 4 0 1
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{
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T 6600 1400 5  10 1 1 0 7 1 1
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pinnumber=io_mem_req_data_ready
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T 6700 1400 5  10 0 1 0 7 1 1
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pinseq=15
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}
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P 6700 1600 7000 1600 4 0 1
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{
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T 6600 1600 5  10 1 1 0 7 1 1
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pinnumber=io_mem_req_cmd_ready
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T 6700 1600 5  10 0 1 0 7 1 1
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pinseq=16
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}
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P 6700 1800 7000 1800 4 0 1
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{
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T 6600 1800 5  10 1 1 0 7 1 1
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pinnumber=io_mem_backup_en
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T 6700 1800 5  10 0 1 0 7 1 1
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pinseq=17
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}
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P 6700 2000 7000 2000 4 0 1
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{
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T 6600 2000 5  10 1 1 0 7 1 1
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pinnumber=io_in_mem_valid
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T 6700 2000 5  10 0 1 0 7 1 1
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pinseq=18
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}
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P 6700 2200 7000 2200 4 0 1
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{
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T 6600 2200 5  10 1 1 0 7 1 1
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pinnumber=io_in_mem_ready
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T 6700 2200 5  10 0 1 0 7 1 1
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pinseq=19
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}

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