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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [mt45w8mw12/] [rtl/] [xml/] [mt45w8mw12_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
mt45w8mw12
def
 
 
 
 
 
 
 

 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 

 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.sim
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
  
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

ADDR_BITS23
DQ_BITS16
MEM_BITS16

 

 
clk
wire
in

 
adv_n
wire
in

 
cre
wire
in

 
o_wait
wire
out

 
 
ce_n
wire
in

 
 
oe_n
wire
in

 
we_n
wire
in

 
 
lb_n
wire
in

 
ub_n
wire
in

 
addr
wire
in
ADDR_BITS-10

 
 
dq
wire
inout
DQ_BITS-10

 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	134	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	134	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	134	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Testbench`
39			`mt45w8mw12`
40			`def`
41	134	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49	134	jt_eaton
50	135	jt_eaton
51			`gen_verilogLib_sim`
52			`105.0`
53			`none`
54			`:Simulation:`
55			`tools/verilog/gen_verilogLib`
56
57
58			`dest_dir`
59			`../views`
60
61
62			`view`
63			`sim`
64
65
66
67	134	jt_eaton
68
69	135	jt_eaton
70			`gen_verilogLib_syn`
71			`105.0`
72			`none`
73			`:Synthesis:`
74			`tools/verilog/gen_verilogLib`
75
76
77			`dest_dir`
78			`../views`
79
80
81			`view`
82			`syn`
83
84
85
86	134	jt_eaton
87
88	135	jt_eaton
89	134	jt_eaton
90
91	135	jt_eaton
92	134	jt_eaton
93	135	jt_eaton
94			`fs-sim`
95	134	jt_eaton
96	135	jt_eaton
97
98			`../verilog/copyright.v`
99			`verilogSourceinclude`
100
101	134	jt_eaton
102	135	jt_eaton
103
104			`../verilog/top.sim`
105			`verilogSourcemodule`
106
107	134	jt_eaton
108	135	jt_eaton
109			`dest_dir../views/sim/`
110			`verilogSourcelibraryDir`
111
112	134	jt_eaton
113
114
115
116	135	jt_eaton
117	134	jt_eaton
118
119	135	jt_eaton
120			`fs-syn`
121	134	jt_eaton
122	135	jt_eaton
123
124			`../verilog/copyright.v`
125			`verilogSourceinclude`
126
127	134	jt_eaton
128	135	jt_eaton
129
130			`../verilog/top.syn`
131			`verilogSourcemodule`
132
133	134	jt_eaton
134	135	jt_eaton
135			`dest_dir../views/syn/`
136			`verilogSourcelibraryDir`
137
138	134	jt_eaton
139
140	135	jt_eaton
141	134	jt_eaton
142
143	135	jt_eaton
144	134	jt_eaton
145
146
147
148
149	135	jt_eaton
150
151	134	jt_eaton
152
153	135	jt_eaton
154			`sim:Simulation:`
155	134	jt_eaton
156	135	jt_eaton	`Verilog`
157
158
159			`fs-sim`
160
161
162	134	jt_eaton
163	135	jt_eaton
164			`syn:Synthesis:`
165	134	jt_eaton
166	135	jt_eaton	`Verilog`
167
168
169			`fs-syn`
170
171
172	134	jt_eaton
173
174	135	jt_eaton
175			`doc`
176
177
178			`ipxact:library="Testbench"`
179			`ipxact:name="toolflow"`
180			`ipxact:version="documentation"/>`
181
182			`:Documentation:`
183			`Verilog`
184
185	134	jt_eaton
186	135	jt_eaton
187	134	jt_eaton
188
189
190	135	jt_eaton
191			`ADDR_BITS23`
192			`DQ_BITS16`
193			`MEM_BITS16`
194
195	134	jt_eaton
196	135	jt_eaton
197	134	jt_eaton
198	135	jt_eaton	`clk`
199			`wire`
200			`in`
201
202	134	jt_eaton
203	135	jt_eaton	`adv_n`
204			`wire`
205			`in`
206
207	134	jt_eaton
208	135	jt_eaton	`cre`
209			`wire`
210			`in`
211
212	134	jt_eaton
213	135	jt_eaton	`o_wait`
214			`wire`
215			`out`
216
217	134	jt_eaton
218
219	135	jt_eaton	`ce_n`
220			`wire`
221			`in`
222
223	134	jt_eaton
224
225	135	jt_eaton	`oe_n`
226			`wire`
227			`in`
228
229	134	jt_eaton
230	135	jt_eaton	`we_n`
231			`wire`
232			`in`
233
234	134	jt_eaton
235
236	135	jt_eaton	`lb_n`
237			`wire`
238			`in`
239
240	134	jt_eaton
241	135	jt_eaton	`ub_n`
242			`wire`
243			`in`
244
245	134	jt_eaton
246	135	jt_eaton	`addr`
247			`wire`
248			`in`
249			`ADDR_BITS-10`
250
251	134	jt_eaton
252
253	135	jt_eaton	`dq`
254			`wire`
255			`inout`
256			`DQ_BITS-10`
257
258	134	jt_eaton
259
260	135	jt_eaton
261	134	jt_eaton
262	135	jt_eaton
263	134	jt_eaton
264
265
266
267
268
269
270
271
272
273
274
275
276
277	135	jt_eaton

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [mt45w8mw12/] [rtl/] [xml/] [mt45w8mw12_def.xml] - Blame information for rev 135