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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [icarus.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
toolflow
icarus
 

 
 

  gen_elab_filelists
  104.0
  none
  
    :*Simulation:*
    :*Synthesis:*
  
  ./tools/sys/gen_elab_child_filelist
  
    
      top_file
      ./TestBench
    
    
      top
    
  

 
 

  gen_filelists
  104.0
  none
  
    :*Simulation:*
    :*Synthesis:*
  
  ./tools/sys/gen_child_filelist
  
    
      top_file
      ./TestBench
    
    
      top
    
  

 
 
 
 

  gen_cov_filelist
  104.0
  none
  
    :*Lint:*
  
  ./tools/sys/gen_child_filelist
  
    
      top_file
      "-v ./TestBench"
    
    
      top
    
    
      suffix
      COV
    
    
      leader
      "-v "
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      view
      syn
    
  

 
 

  gen_verilogLib_lint
  105.0
  none
  :*Lint:*
  ./tools/verilog/gen_verilogLib
    
    
      view
      lint
    
  

 

 
 
 

 
 
 
 
 
   
      fs-sim
 
      
        dest_dir
        ../views/sim/
        verilogSource
        libraryDir
      
 
   
 
 
 
 
   
      fs-syn
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
 
   
      fs-lint
 
      
        dest_dir
        ../views/lint/
        verilogSource
        libraryDir
      
 
   
 
 
 
 
 
 
 

 
 
 
 
 
 

 
     
        PERIOD40
        TIMEOUT100000
      
 
 
 
       
 
 
              
              Bfm
              
                                   spirit:library="Testbench"
                                   spirit:name="clock_gen"
                                   spirit:version="bfm.design"/>
              
 
 
              
              sim
              :*Simulation:*
              Verilog
              
              fs-sim
              
 
 
              
              syn
              :*Synthesis:*
              Verilog
              
              fs-syn
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              
              fs-lint
              
 
 
 
 
      
 
 
 
 
 
 
 
 
 
 
 
 
 

 
clk
  wire
  in

 
START
  wire
  in

 
 
FAIL
  wire
  out

 
 
 
FINISH
  wire
  out

 
 

 

 

 
 
 
 
 
 

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [icarus.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`toolflow`
40			`icarus`
41
42
43
44
45
46	134	jt_eaton	`gen_elab_filelists`
47			`104.0`
48			`none`
49
50			`:Simulation:`
51			`:Synthesis:`
52
53			`./tools/sys/gen_elab_child_filelist`
54
55
56			`top_file`
57			`./TestBench`
58
59
60			`top`
61
62
63
64
65
66
67	131	jt_eaton	`gen_filelists`
68			`104.0`
69			`none`
70
71			`:Simulation:`
72			`:Synthesis:`
73
74			`./tools/sys/gen_child_filelist`
75
76
77			`top_file`
78			`./TestBench`
79
80
81			`top`
82
83
84
85
86
87	134	jt_eaton
88
89	131	jt_eaton
90			`gen_cov_filelist`
91			`104.0`
92			`none`
93
94			`:Lint:`
95
96			`./tools/sys/gen_child_filelist`
97
98
99			`top_file`
100			`"-v ./TestBench"`
101
102
103			`top`
104
105
106			`suffix`
107			`COV`
108
109
110			`leader`
111			`"-v "`
112
113
114
115
116
117
118
119
120			`gen_verilogLib_sim`
121			`105.0`
122			`none`
123			`:Simulation:`
124			`./tools/verilog/gen_verilogLib`
125
126
127			`view`
128			`sim`
129
130
131
132
133
134
135			`gen_verilogLib_syn`
136			`105.0`
137			`none`
138			`:Synthesis:`
139			`./tools/verilog/gen_verilogLib`
140
141
142			`view`
143			`syn`
144
145
146
147
148
149
150			`gen_verilogLib_lint`
151			`105.0`
152			`none`
153			`:Lint:`
154			`./tools/verilog/gen_verilogLib`
155
156
157			`view`
158			`lint`
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174			`fs-sim`
175
176
177			`dest_dir`
178			`../views/sim/`
179			`verilogSource`
180			`libraryDir`
181
182
183
184
185
186
187
188
189			`fs-syn`
190
191
192			`dest_dir`
193			`../views/syn/`
194			`verilogSource`
195			`libraryDir`
196
197
198
199
200
201
202
203			`fs-lint`
204
205
206			`dest_dir`
207			`../views/lint/`
208			`verilogSource`
209			`libraryDir`
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230			`PERIOD40`
231			`TIMEOUT100000`
232
233
234
235
236
237
238
239
240			`Bfm`
241
242			`spirit:library="Testbench"`
243			`spirit:name="clock_gen"`
244			`spirit:version="bfm.design"/>`
245
246
247
248
249			`sim`
250			`:Simulation:`
251			`Verilog`
252
253			`fs-sim`
254
255
256
257
258			`syn`
259			`:Synthesis:`
260			`Verilog`
261
262			`fs-syn`
263
264
265
266
267
268			`lint`
269			`:Lint:`
270			`Verilog`
271
272			`fs-lint`
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294			`clk`
295			`wire`
296			`in`
297
298
299			`START`
300			`wire`
301			`in`
302
303
304
305			`FAIL`
306			`wire`
307			`out`
308
309
310
311
312			`FINISH`
313			`wire`
314			`out`
315
316
317
318
319
320
321
322
323
324
325
326
327
328