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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [ise.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
toolflow
ise
 

 
 

  gen_root
  103.5
  none
  :*Simulation:*
  ./tools/verilog/gen_root

 
 
 

  gen_design
  103.5
  none
  :*Simulation:*
  ./tools/verilog/gen_design

 
 
 
 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 
 
 
 
 
 
 
 
 
 

 
 
 

 
 
 
 
 
 
   
      fs-syn
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
 
 

 
 
 
 
 
 

 
 
 
 
       
 
 
 
              
              syn
              :*Synthesis:*
              Verilog
              
              fs-syn
              
 
 
 
 
      
 
 
 

 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`toolflow`
40			`ise`
41
42
43
44
45	133	jt_eaton
46			`gen_root`
47			`103.5`
48			`none`
49			`:Simulation:`
50			`./tools/verilog/gen_root`
51
52	131	jt_eaton
53
54
55
56	133	jt_eaton	`gen_design`
57			`103.5`
58			`none`
59			`:Simulation:`
60			`./tools/verilog/gen_design`
61
62
63
64
65
66
67
68
69	131	jt_eaton	`gen_verilogLib_syn`
70			`105.0`
71			`none`
72			`:Synthesis:`
73			`./tools/verilog/gen_verilogLib`
74
75
76			`dest_dir`
77			`../views`
78
79
80			`view`
81			`syn`
82
83
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109			`fs-syn`
110
111
112			`dest_dir`
113			`../views/syn/`
114			`verilogSource`
115			`libraryDir`
116
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140			`syn`
141			`:Synthesis:`
142			`Verilog`
143
144			`fs-syn`
145
146
147
148
149
150
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [ise.xml] - Blame information for rev 133