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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [rtl_check.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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Testbench
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toolflow
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rtl_check
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  gen_filelists
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  104.0
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  none
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    :*Lint:*
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  tools/sys/gen_child_filelist
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      top
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      top_file
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      ./TestBench
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  gen_verilog
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  gen_verilogLib_lint
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  tools/verilog/gen_verilogLib
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      view
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      lint
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  gen_yosys_filelist
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      suffix
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      leader
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      "read_verilog "
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      fs-lint
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        dest_dir
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        ../views/lint/
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        verilogSource
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        libraryDir
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              lint
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              Verilog
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clk
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  wire
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  in
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reset
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  wire
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  in
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STOP
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  wire
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  out
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BAD
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  wire
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  out
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