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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [rtl_check.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
toolflow
rtl_check
 

 
 
 

  gen_filelists
  104.0
  none
  
    :*Lint:*
  
  ./tools/sys/gen_child_filelist
    
    
      top
    
    
      top_file
      ./TestBench
    
  

 
 
 

  gen_verilog
  104.0
  none
  :*Lint:*
  ./tools/verilog/gen_verilog
  
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 
 

  gen_verilogLib_lint
  105.0
  none
  :*Lint:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      lint
    
  

 
 
 
 

 
 

 
 
   
      fs-lint
 
      
        dest_dir
        ../views/lint/
        verilogSource
        libraryDir
      
 
   
 
 

 

 
       
 
              
              lint
              :*Lint:*
              Verilog
              
              fs-lint
              
 
      
 
 

 
clk
  wire
  in

 
reset
  wire
  in

 
 
STOP
  wire
  out

 
 
BAD
  wire
  out

 
 
 
 

 
 
 
 
 

 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`toolflow`
40			`rtl_check`
41
42
43
44
45
46
47			`gen_filelists`
48			`104.0`
49			`none`
50
51			`:Lint:`
52
53			`./tools/sys/gen_child_filelist`
54
55
56			`top`
57
58
59			`top_file`
60			`./TestBench`
61
62
63
64
65
66
67
68			`gen_verilog`
69			`104.0`
70			`none`
71			`:Lint:`
72			`./tools/verilog/gen_verilog`
73
74
75			`dest_dir`
76			`../verilog`
77
78
79			`top`
80
81
82
83
84
85
86
87
88			`gen_verilogLib_lint`
89			`105.0`
90			`none`
91			`:Lint:`
92			`./tools/verilog/gen_verilogLib`
93
94
95			`dest_dir`
96			`../views`
97
98
99			`view`
100			`lint`
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115			`fs-lint`
116
117
118			`dest_dir`
119			`../views/lint/`
120			`verilogSource`
121			`libraryDir`
122
123
124
125
126
127
128
129
130
131
132
133
134			`lint`
135			`:Lint:`
136			`Verilog`
137
138			`fs-lint`
139
140
141
142
143
144
145
146			`clk`
147			`wire`
148			`in`
149
150
151			`reset`
152			`wire`
153			`in`
154
155
156
157			`STOP`
158			`wire`
159			`out`
160
161
162
163			`BAD`
164			`wire`
165			`out`
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [rtl_check.xml] - Blame information for rev 131