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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilator.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
toolflow
verilator
 

 
 

  gen_filelists
  104.0
  none
  
    :*Synthesis:*
  
  ./tools/sys/gen_child_filelist
    
    
      top_file
      "./TestBench"
    
    
      top
    
  

 
 

  gen_cov_filelist
  104.0
  none
  
    :*Lint:*
  
  ./tools/sys/gen_child_filelist
  
    
      top_file
      "-v ./TestBench"
    
    
      top
    
    
      suffix
      COV
    
    
      leader
      "-v "
    
  

 
 
 
 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

  gen_verilogLib_lint
  105.0
  none
  :*Lint:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      lint
    
  

 
 
 
 
 
 
 

 
 
 

 
 
   
      fs-syn
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
   
      fs-lint
 
      
        dest_dir
        ../views/lint/
        verilogSource
        libraryDir
      
 
   
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 

 
      
        PERIOD40
        TIMEOUT100000
      
 
    
 
              
              Bfm
              
                                   spirit:library="Testbench"
                                   spirit:name="clock_gen"
                                   spirit:version="bfm.design"/>
              
 
 
              
              syn
              :*Synthesis:*
              Verilog
              
              fs-syn
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              
              fs-lint
              
 
 
 
 
 
    
 
 
 
    
 
      clk
        wire
        in
      
 
      START
        wire
        in
      
 
 
      FAIL
        reg
        out
      
 
 
      FINISH
        reg
        out
      
 
    
 
 

 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilator.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`toolflow`
40			`verilator`
41
42
43
44
45
46			`gen_filelists`
47			`104.0`
48			`none`
49
50			`:Synthesis:`
51
52			`./tools/sys/gen_child_filelist`
53
54
55			`top_file`
56			`"./TestBench"`
57
58
59			`top`
60
61
62
63
64
65
66			`gen_cov_filelist`
67			`104.0`
68			`none`
69
70			`:Lint:`
71
72			`./tools/sys/gen_child_filelist`
73
74
75			`top_file`
76			`"-v ./TestBench"`
77
78
79			`top`
80
81
82			`suffix`
83			`COV`
84
85
86			`leader`
87			`"-v "`
88
89
90
91
92
93
94
95
96
97
98			`gen_verilogLib_syn`
99			`105.0`
100			`none`
101			`:Synthesis:`
102			`./tools/verilog/gen_verilogLib`
103
104
105			`dest_dir`
106			`../views`
107
108
109			`view`
110			`syn`
111
112
113
114
115
116
117
118			`gen_verilogLib_lint`
119			`105.0`
120			`none`
121			`:Lint:`
122			`./tools/verilog/gen_verilogLib`
123
124
125			`dest_dir`
126			`../views`
127
128
129			`view`
130			`lint`
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149			`fs-syn`
150
151
152			`dest_dir`
153			`../views/syn/`
154			`verilogSource`
155			`libraryDir`
156
157
158
159
160
161
162			`fs-lint`
163
164
165			`dest_dir`
166			`../views/lint/`
167			`verilogSource`
168			`libraryDir`
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191			`PERIOD40`
192			`TIMEOUT100000`
193
194
195
196
197
198			`Bfm`
199
200			`spirit:library="Testbench"`
201			`spirit:name="clock_gen"`
202			`spirit:version="bfm.design"/>`
203
204
205
206
207			`syn`
208			`:Synthesis:`
209			`Verilog`
210
211			`fs-syn`
212
213
214
215
216
217			`lint`
218			`:Lint:`
219			`Verilog`
220
221			`fs-lint`
222
223
224
225
226
227
228
229
230
231
232
233
234			`clk`
235			`wire`
236			`in`
237
238
239			`START`
240			`wire`
241			`in`
242
243
244
245			`FAIL`
246			`reg`
247			`out`
248
249
250
251			`FINISH`
252			`reg`
253			`out`
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269