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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilog.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
toolflow
verilog
 

 
 
 

  gen_root
  103.5
  none
  :*Simulation:*
  ./tools/verilog/gen_root

 
 
 

  gen_design
  103.5
  none
  :*Simulation:*
  ./tools/verilog/gen_design

 
 
 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 
 
 
 
 
 
 
 
 
 

 
 
 

 
 
 
 
 
   
      fs-sim
 
      
        dest_dir
        ../views/sim/
        verilogSource
        libraryDir
      
 
   
 
 
 
   
      fs-syn
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
   
      fs-lint
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
 
 
 
 

 
 
 
 
 
 

 
 
 
 
       
 
 
 
 
              
              sim
              :*Simulation:*
              Verilog
              
              fs-sim
              
 
 
              
              syn
              :*Synthesis:*
              Verilog
              
              fs-syn
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              
              fs-lint
              
 
 
 
 
 
 
 
 
      
 
 
 

 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilog.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`toolflow`
40			`verilog`
41
42
43
44
45
46	133	jt_eaton
47			`gen_root`
48			`103.5`
49			`none`
50			`:Simulation:`
51			`./tools/verilog/gen_root`
52
53	131	jt_eaton
54
55	133	jt_eaton
56	131	jt_eaton
57	133	jt_eaton	`gen_design`
58			`103.5`
59			`none`
60			`:Simulation:`
61			`./tools/verilog/gen_design`
62
63
64
65
66
67
68
69
70	131	jt_eaton	`gen_verilogLib_sim`
71			`105.0`
72			`none`
73			`:Simulation:`
74			`./tools/verilog/gen_verilogLib`
75
76
77			`dest_dir`
78			`../views`
79
80
81			`view`
82			`sim`
83
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90			`gen_verilogLib_syn`
91			`105.0`
92			`none`
93			`:Synthesis:`
94			`./tools/verilog/gen_verilogLib`
95
96
97			`dest_dir`
98			`../views`
99
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101			`view`
102			`syn`
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129			`fs-sim`
130
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132			`dest_dir`
133			`../views/sim/`
134			`verilogSource`
135			`libraryDir`
136
137
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142
143			`fs-syn`
144
145
146			`dest_dir`
147			`../views/syn/`
148			`verilogSource`
149			`libraryDir`
150
151
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153
154
155
156			`fs-lint`
157
158
159			`dest_dir`
160			`../views/syn/`
161			`verilogSource`
162			`libraryDir`
163
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190			`sim`
191			`:Simulation:`
192			`Verilog`
193
194			`fs-sim`
195
196
197
198
199			`syn`
200			`:Synthesis:`
201			`Verilog`
202
203			`fs-syn`
204
205
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208
209			`lint`
210			`:Lint:`
211			`Verilog`
212
213			`fs-lint`
214
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