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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilog.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Testbench
toolflow
verilog
 

 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      view
      syn
    
  

 
 
 
 
 
 
 
 
 
 
 
 

 
 
 

 
 
 
 
 
   
      fs-sim
 
      
        dest_dir
        ../views/sim/
        verilogSource
        libraryDir
      
 
   
 
 
 
   
      fs-syn
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
   
      fs-lint
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
 
 
 
 

 
 
 
 
 
 

 
 
 
 
       
 
 
 
 
              
              sim
              :*Simulation:*
              Verilog
              
              fs-sim
              
 
 
              
              syn
              :*Synthesis:*
              Verilog
              
              fs-syn
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              
              fs-lint
              
 
 
 
 
 
 
 
 
      
 
 
 

 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`toolflow`
40			`verilog`
41
42
43
44
45	133	jt_eaton
46	131	jt_eaton	`gen_verilogLib_sim`
47			`105.0`
48			`none`
49			`:Simulation:`
50			`./tools/verilog/gen_verilogLib`
51
52
53			`view`
54			`sim`
55
56
57
58
59
60
61
62			`gen_verilogLib_syn`
63			`105.0`
64			`none`
65			`:Synthesis:`
66			`./tools/verilog/gen_verilogLib`
67
68
69			`view`
70			`syn`
71
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97			`fs-sim`
98
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100			`dest_dir`
101			`../views/sim/`
102			`verilogSource`
103			`libraryDir`
104
105
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111			`fs-syn`
112
113
114			`dest_dir`
115			`../views/syn/`
116			`verilogSource`
117			`libraryDir`
118
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123
124			`fs-lint`
125
126
127			`dest_dir`
128			`../views/syn/`
129			`verilogSource`
130			`libraryDir`
131
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158			`sim`
159			`:Simulation:`
160			`Verilog`
161
162			`fs-sim`
163
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167			`syn`
168			`:Synthesis:`
169			`Verilog`
170
171			`fs-syn`
172
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176
177			`lint`
178			`:Lint:`
179			`Verilog`
180
181			`fs-lint`
182
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilog.xml] - Blame information for rev 134