URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [doc/] [sch/] [cde_clock_gater.sch] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton	`v 20121203 2`
2			`C 1600 4300 1 0 0 in_port.sym`
3			`{`
4			`T 2100 4100 5 10 1 1 0 6 1`
5			`refdes=enable`
6			`}`
7			`C 1600 2800 1 0 0 in_port.sym`
8			`{`
9			`T 1900 2600 5 10 1 1 0 6 1`
10			`refdes=clk_in`
11			`}`
12			`C 1600 4700 1 0 0 in_port.sym`
13			`{`
14			`T 2300 5100 5 10 1 1 0 6 1`
15			`refdes=atg_clk_mode`
16			`}`
17			`C 8200 4300 1 0 0 out_port.sym`
18			`{`
19			`T 9200 4300 5 10 1 1 0 0 1`
20			`refdes=clk_out`
21			`}`
22			`C 4500 3000 1 0 0 latch.sym`
23			`{`
24			`T 6300 4800 5 10 0 0 0 0 1`
25			`device=LATCH`
26			`T 5800 5000 5 10 1 1 0 6 1`
27			`refdes=U?`
28			`}`
29			`C 6700 4100 1 0 0 and2-1.sym`
30			`{`
31			`T 7100 4000 5 10 1 1 0 2 1`
32			`refdes=U?`
33			`T 7100 4200 5 8 0 0 0 0 1`
34			`device=and`
35			`}`
36			`C 3000 3100 1 0 0 not-1.sym`
37			`{`
38			`T 3200 4100 5 10 0 0 0 0 1`
39			`device=not`
40			`T 3500 3400 5 10 1 1 0 2 1`
41			`refdes=U?`
42			`}`
43			`N 8200 4400 8000 4400 4`
44			`N 4100 3600 4500 3600 4`
45			`N 2500 2900 6700 2900 4`
46			`N 6700 4600 6100 4600 4`
47			`N 3000 3600 3000 2900 4`
48			`C 3000 4300 1 0 0 or2-1.sym`
49			`{`
50			`T 3400 4200 5 10 1 1 0 2 1`
51			`refdes=U?`
52			`T 3400 4400 5 8 0 0 0 0 1`
53			`device=or`
54			`}`
55			`N 3000 4400 2500 4400 4`
56			`N 3000 4800 2500 4800 4`
57			`N 4500 4600 4300 4600 4`
58			`N 6700 4200 6700 2900 4`