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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [doc/] [sch/] [cde_clock_sys.sch] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
v 20100214 1
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C 1400 300 1 0 0 in_port.sym
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{
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T 1400 300 5 10 1 1 0 6 1 1
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refdes=pwron_pad_in
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}
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C 1400 700 1 0 0 in_port.sym
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{
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T 1400 700 5 10 1 1 0 6 1 1
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refdes=b_clk_pad_in
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}
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C 1400 1100 1 0 0 in_port.sym
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{
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T 1400 1100 5 10 1 1 0 6 1 1
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refdes=a_clk_pad_in
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}
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C 3800 300  1 0 0 out_port.sym
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{
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T 4800 300 5  10 1 1 0 0 1 1
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refdes=reset
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}
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C 3800 700  1 0 0 out_port.sym
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{
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T 4800 700 5  10 1 1 0 0 1 1
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refdes=one_usec
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}
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C 3800 1100  1 0 0 out_port.sym
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{
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T 4800 1100 5  10 1 1 0 0 1 1
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refdes=div_clk_out
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}

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