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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_gater] - Blame information for rev 134

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wire  latch_enable;
reg   latch_output;
 
assign latch_enable = enable | atg_clk_mode;
 
always @(latch_enable or clk_in)
begin
  if (~clk_in)
     latch_output = latch_enable;
  else
     latch_output = latch_output;
end
 
assign clk_out = latch_output && clk_in;
 
 
 

Line No.	Rev	Author	Line
1	134	jt_eaton
2
3			`wire latch_enable;`
4			`reg latch_output;`
5
6			`assign latch_enable = enable \| atg_clk_mode;`
7
8			`always @(latch_enable or clk_in)`
9			`begin`
10			`if (~clk_in)`
11			`latch_output = latch_enable;`
12			`else`
13			`latch_output = latch_output;`
14			`end`
15
16			`assign clk_out = latch_output && clk_in;`
17
18
19

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_gater] - Blame information for rev 134