URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_gater.v] - Blame information for rev 131

Details | Compare with Previous | View Log


/**********************************************************************/
/*                                                                    */
/*                                                                    */
/*   Copyright (c) 2012 Ouabache Design Works                         */
/*                                                                    */
/*          All Rights Reserved Worldwide                             */
/*                                                                    */
/*   Licensed under the Apache License,Version2.0 (the'License');     */
/*   you may not use this file except in compliance with the License. */
/*   You may obtain a copy of the License at                          */
/*                                                                    */
/*       http://www.apache.org/licenses/LICENSE-2.0                   */
/*                                                                    */
/*   Unless required by applicable law or agreed to in                */
/*   writing, software distributed under the License is               */
/*   distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES              */
/*   OR CONDITIONS OF ANY KIND, either express or implied.            */
/*   See the License for the specific language governing              */
/*   permissions and limitations under the License.                   */
/**********************************************************************/
 
module cde_clock_gater (
                input  wire  clk_in,
                input  wire  enable,
                input  wire  atg_clk_mode,
                output wire  clk_out
               );
 
 
wire  latch_enable;
reg   latch_output;
 
assign latch_enable = enable | atg_clk_mode;
 
always @(latch_enable or clk_in)
begin
  if (~clk_in)
     latch_output = latch_enable;
  else
     latch_output = latch_output;
end
 
assign clk_out = latch_output && clk_in;
 
 
 
 
endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton	`/**********************************************************************/`
2			`/* */`
3			`/* */`
4			`/* Copyright (c) 2012 Ouabache Design Works */`
5			`/* */`
6			`/* All Rights Reserved Worldwide */`
7			`/* */`
8			`/* Licensed under the Apache License,Version2.0 (the'License'); */`
9			`/* you may not use this file except in compliance with the License. */`
10			`/* You may obtain a copy of the License at */`
11			`/* */`
12			`/* http://www.apache.org/licenses/LICENSE-2.0 */`
13			`/* */`
14			`/* Unless required by applicable law or agreed to in */`
15			`/* writing, software distributed under the License is */`
16			`/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */`
17			`/* OR CONDITIONS OF ANY KIND, either express or implied. */`
18			`/* See the License for the specific language governing */`
19			`/* permissions and limitations under the License. */`
20			`/**********************************************************************/`
21
22			`module cde_clock_gater (`
23			`input wire clk_in,`
24			`input wire enable,`
25			`input wire atg_clk_mode,`
26			`output wire clk_out`
27			`);`
28
29
30			`wire latch_enable;`
31			`reg latch_output;`
32
33			`assign latch_enable = enable \| atg_clk_mode;`
34
35			`always @(latch_enable or clk_in)`
36			`begin`
37			`if (~clk_in)`
38			`latch_output = latch_enable;`
39			`else`
40			`latch_output = latch_output;`
41			`end`
42
43			`assign clk_out = latch_output && clk_in;`
44
45
46
47
48			`endmodule`

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_gater.v] - Blame information for rev 131