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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_sys] - Blame information for rev 134

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reg [6:0]  counter;
reg [3:0]  reset_cnt;
 
 
 
always@(posedge ckIn or posedge pwron_reset)
if(pwron_reset)  pwron_reset_n <= 1'b0;
else             pwron_reset_n <= 1'b1;
 
 
generate
 
if( CLOCK_SRC)
 
  begin
  assign ckIn = b_clk_pad_in;
  end
else
  begin
  assign ckIn = a_clk_pad_in;
  end
 
endgenerate
 
 
generate
 
if( RESET_SENSE)
 
  begin
  assign pwron_reset = !pwron_pad_in;
  end
else
  begin
  assign pwron_reset = pwron_pad_in;
  end
 
endgenerate
 
 
 
 
 
 
 
 
 
always@(posedge ckIn or posedge pwron_reset)
  if( pwron_reset)   reset_cnt     <= 4'b1111;
  else
  if(|reset_cnt)     reset_cnt     <= reset_cnt-4'b0001;
  else               reset_cnt     <= 4'b0000;
 
 
 
always@(posedge ckIn or posedge pwron_reset)
  if( pwron_reset)   ref_reset     <= 1'b1;
  else               ref_reset     <= |reset_cnt;
 
 
always@(posedge dll_clk)
  if(dll_reset)
       begin
       one_usec  <=  1'b0;
       counter   <=  FREQ*PLL_MULT/2;
       end
  else if(counter == 7'b0000001)
       begin
       one_usec  <= !one_usec;
       counter   <=  FREQ*PLL_MULT/2;
       end
  else
       begin
       one_usec  <=  one_usec;
       counter   <=  counter -7'b0000001;
       end
 

Line No.	Rev	Author	Line
1	134	jt_eaton
2			`reg [6:0] counter;`
3			`reg [3:0] reset_cnt;`
4
5
6
7			`always@(posedge ckIn or posedge pwron_reset)`
8			`if(pwron_reset) pwron_reset_n <= 1'b0;`
9			`else pwron_reset_n <= 1'b1;`
10
11
12			`generate`
13
14			`if( CLOCK_SRC)`
15
16			`begin`
17			`assign ckIn = b_clk_pad_in;`
18			`end`
19			`else`
20			`begin`
21			`assign ckIn = a_clk_pad_in;`
22			`end`
23
24			`endgenerate`
25
26
27			`generate`
28
29			`if( RESET_SENSE)`
30
31			`begin`
32			`assign pwron_reset = !pwron_pad_in;`
33			`end`
34			`else`
35			`begin`
36			`assign pwron_reset = pwron_pad_in;`
37			`end`
38
39			`endgenerate`
40
41
42
43
44
45
46
47
48
49			`always@(posedge ckIn or posedge pwron_reset)`
50			`if( pwron_reset) reset_cnt <= 4'b1111;`
51			`else`
52			`if(\|reset_cnt) reset_cnt <= reset_cnt-4'b0001;`
53			`else reset_cnt <= 4'b0000;`
54
55
56
57			`always@(posedge ckIn or posedge pwron_reset)`
58			`if( pwron_reset) ref_reset <= 1'b1;`
59			`else ref_reset <= \|reset_cnt;`
60
61
62			`always@(posedge dll_clk)`
63			`if(dll_reset)`
64			`begin`
65			`one_usec <= 1'b0;`
66			`counter <= FREQ*PLL_MULT/2;`
67			`end`
68			`else if(counter == 7'b0000001)`
69			`begin`
70			`one_usec <= !one_usec;`
71			`counter <= FREQ*PLL_MULT/2;`
72			`end`
73			`else`
74			`begin`
75			`one_usec <= one_usec;`
76			`counter <= counter -7'b0000001;`
77			`end`
78

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_sys] - Blame information for rev 134