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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_sys.v] - Blame information for rev 134

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1 131 jt_eaton
/**********************************************************************/
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/*                                                                    */
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/*                                                                    */
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/*   Copyright (c) 2012 Ouabache Design Works                         */
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/*                                                                    */
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/*          All Rights Reserved Worldwide                             */
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/*                                                                    */
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/*   Licensed under the Apache License,Version2.0 (the'License');     */
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/*   you may not use this file except in compliance with the License. */
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/*   You may obtain a copy of the License at                          */
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/*                                                                    */
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/*       http://www.apache.org/licenses/LICENSE-2.0                   */
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/*                                                                    */
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/*   Unless required by applicable law or agreed to in                */
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/*   writing, software distributed under the License is               */
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/*   distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES              */
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/*   OR CONDITIONS OF ANY KIND, either express or implied.            */
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/*   See the License for the specific language governing              */
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/*   permissions and limitations under the License.                   */
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/**********************************************************************/
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module
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cde_clock_sys
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#(parameter   FREQ        = 48,
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              PLL_MULT    =  2,
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              PLL_DIV     =  4,
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              PLL_SIZE    =  4,
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              CLOCK_SRC   =  0,
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              RESET_SENSE =  0
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)
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(
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input  wire   a_clk_pad_in,
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input  wire   b_clk_pad_in,
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input  wire   pwron_pad_in,
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output  wire  div_clk_out,
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output  reg   one_usec,
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output  wire  reset
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);
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wire       ckIn;
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wire       dll_clk;
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reg        ref_reset;
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reg [6:0]  counter;
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reg [3:0]  reset_cnt;
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wire       pwron_reset;
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wire       pwron_reset_n;
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wire       dll_reset;
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assign pwron_reset_n = !pwron_reset;
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generate
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if( CLOCK_SRC)
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  begin
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  assign ckIn = b_clk_pad_in;
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  end
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else
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  begin
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  assign ckIn = a_clk_pad_in;
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  end
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endgenerate
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generate
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if( RESET_SENSE)
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  begin
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  assign pwron_reset = !pwron_pad_in;
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  end
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else
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  begin
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  assign pwron_reset = pwron_pad_in;
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  end
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endgenerate
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always@(posedge ckIn or posedge pwron_reset)
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  if( pwron_reset)   reset_cnt     <= 4'b1111;
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  else
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  if(|reset_cnt)     reset_cnt     <= reset_cnt-4'b0001;
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  else               reset_cnt     <= 4'b0000;
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always@(posedge ckIn or posedge pwron_reset)
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  if( pwron_reset)   ref_reset     <= 1'b1;
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  else               ref_reset     <= |reset_cnt;
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always@(posedge dll_clk)
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  if(dll_reset)
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       begin
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       one_usec  <=  1'b0;
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       counter   <=  FREQ*PLL_MULT/2;
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       end
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  else if(counter == 7'b0000001)
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       begin
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       one_usec  <= !one_usec;
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       counter   <=  FREQ*PLL_MULT/2;
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       end
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  else
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       begin
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       one_usec  <=  one_usec;
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       counter   <=  counter -7'b0000001;
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       end
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cde_clock_dll
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  #(.MULT   (PLL_MULT),
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    .DIV    (PLL_DIV),
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    .SIZE   (PLL_SIZE)
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   )
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dll (
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        .ref_clk            (ckIn),
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        .reset              (pwron_reset),
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        .dll_clk_out        (dll_clk),
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        .div_clk_out        (div_clk_out)
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    );
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cde_sync_with_reset
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  #(.WIDTH  (1),
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    .DEPTH  (2),
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    .RST_VAL(1'b1)
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   )
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  ref_rsync(
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    .clk                 (div_clk_out),
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    .reset_n             (pwron_reset_n),
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    .data_in             (ref_reset),
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    .data_out            (reset)
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       );
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cde_sync_with_reset
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  #(.WIDTH  (1),
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    .DEPTH  (2),
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    .RST_VAL(1'b1)
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   )
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  dll_rsync(
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    .clk                 (dll_clk),
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    .reset_n             (pwron_reset_n),
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    .data_in             (ref_reset),
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    .data_out            (dll_reset)
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       );
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endmodule

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