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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_sys.v] - Blame information for rev 131

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/**********************************************************************/
/*                                                                    */
/*                                                                    */
/*   Copyright (c) 2012 Ouabache Design Works                         */
/*                                                                    */
/*          All Rights Reserved Worldwide                             */
/*                                                                    */
/*   Licensed under the Apache License,Version2.0 (the'License');     */
/*   you may not use this file except in compliance with the License. */
/*   You may obtain a copy of the License at                          */
/*                                                                    */
/*       http://www.apache.org/licenses/LICENSE-2.0                   */
/*                                                                    */
/*   Unless required by applicable law or agreed to in                */
/*   writing, software distributed under the License is               */
/*   distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES              */
/*   OR CONDITIONS OF ANY KIND, either express or implied.            */
/*   See the License for the specific language governing              */
/*   permissions and limitations under the License.                   */
/**********************************************************************/
 
module
cde_clock_sys
#(parameter   FREQ        = 48,
              PLL_MULT    =  2,
              PLL_DIV     =  4,
              PLL_SIZE    =  4,
              CLOCK_SRC   =  0,
              RESET_SENSE =  0
)
 
(
input  wire   a_clk_pad_in,
input  wire   b_clk_pad_in,
input  wire   pwron_pad_in,
 
 
output  wire  div_clk_out,
 
output  reg   one_usec,
output  wire   reset
 
);
 
wire       ckIn;
wire       dll_clk;
 
reg        ref_reset;
 
reg [6:0]  counter;
reg [3:0]  reset_cnt;
 
wire       pwron_reset;
wire       dll_reset;
 
 
generate
 
if( CLOCK_SRC)
 
  begin
  assign ckIn = b_clk_pad_in;
  end
else
  begin
  assign ckIn = a_clk_pad_in;
  end
 
endgenerate
 
 
generate
 
if( RESET_SENSE)
 
  begin
  assign pwron_reset = !pwron_pad_in;
  end
else
  begin
  assign pwron_reset = pwron_pad_in;
  end
 
endgenerate
 
 
 
 
 
 
 
 
 
always@(posedge ckIn or posedge pwron_reset)
  if( pwron_reset)   reset_cnt     <= 4'b1111;
  else
  if(|reset_cnt)     reset_cnt     <= reset_cnt-4'b0001;
  else               reset_cnt     <= 4'b0000;
 
 
 
always@(posedge ckIn or posedge pwron_reset)
  if( pwron_reset)   ref_reset     <= 1'b1;
  else               ref_reset     <= |reset_cnt;
 
 
always@(posedge dll_clk)
  if(dll_reset)
       begin
       one_usec  <=  1'b0;
       counter   <=  FREQ*PLL_MULT/2;
       end
  else if(counter == 7'b0000001)
       begin
       one_usec  <= !one_usec;
       counter   <=  FREQ*PLL_MULT/2;
       end
  else
       begin
       one_usec  <=  one_usec;
       counter   <=  counter -7'b0000001;
       end
 
 
 
cde_clock_dll
  #(.MULT   (PLL_MULT),
    .DIV    (PLL_DIV),
    .SIZE   (PLL_SIZE)
   )
dll (
        .ref_clk            (ckIn),
        .reset              (pwron_reset),
        .dll_clk_out        (dll_clk),
        .div_clk_out        (div_clk_out)
    );
 
 
 
cde_sync_with_reset
  #(.WIDTH  (1),
    .DEPTH  (2),
    .RST_VAL(1'b1)
   )
  ref_rsync(
    .clk                 (div_clk_out),
    .reset_n             (!pwron_reset),
    .data_in             (ref_reset),
    .data_out            (reset)
       );
 
 
cde_sync_with_reset
  #(.WIDTH  (1),
    .DEPTH  (2),
    .RST_VAL(1'b1)
   )
  dll_rsync(
    .clk                 (dll_clk),
    .reset_n             (!pwron_reset),
    .data_in             (ref_reset),
    .data_out            (dll_reset)
       );
 
 
 
endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton	`/**********************************************************************/`
2			`/* */`
3			`/* */`
4			`/* Copyright (c) 2012 Ouabache Design Works */`
5			`/* */`
6			`/* All Rights Reserved Worldwide */`
7			`/* */`
8			`/* Licensed under the Apache License,Version2.0 (the'License'); */`
9			`/* you may not use this file except in compliance with the License. */`
10			`/* You may obtain a copy of the License at */`
11			`/* */`
12			`/* http://www.apache.org/licenses/LICENSE-2.0 */`
13			`/* */`
14			`/* Unless required by applicable law or agreed to in */`
15			`/* writing, software distributed under the License is */`
16			`/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */`
17			`/* OR CONDITIONS OF ANY KIND, either express or implied. */`
18			`/* See the License for the specific language governing */`
19			`/* permissions and limitations under the License. */`
20			`/**********************************************************************/`
21
22			`module`
23			`cde_clock_sys`
24			`#(parameter FREQ = 48,`
25			`PLL_MULT = 2,`
26			`PLL_DIV = 4,`
27			`PLL_SIZE = 4,`
28			`CLOCK_SRC = 0,`
29			`RESET_SENSE = 0`
30			`)`
31
32			`(`
33			`input wire a_clk_pad_in,`
34			`input wire b_clk_pad_in,`
35			`input wire pwron_pad_in,`
36
37
38			`output wire div_clk_out,`
39
40			`output reg one_usec,`
41			`output wire reset`
42
43			`);`
44
45			`wire ckIn;`
46			`wire dll_clk;`
47
48			`reg ref_reset;`
49
50			`reg [6:0] counter;`
51			`reg [3:0] reset_cnt;`
52
53			`wire pwron_reset;`
54			`wire dll_reset;`
55
56
57			`generate`
58
59			`if( CLOCK_SRC)`
60
61			`begin`
62			`assign ckIn = b_clk_pad_in;`
63			`end`
64			`else`
65			`begin`
66			`assign ckIn = a_clk_pad_in;`
67			`end`
68
69			`endgenerate`
70
71
72			`generate`
73
74			`if( RESET_SENSE)`
75
76			`begin`
77			`assign pwron_reset = !pwron_pad_in;`
78			`end`
79			`else`
80			`begin`
81			`assign pwron_reset = pwron_pad_in;`
82			`end`
83
84			`endgenerate`
85
86
87
88
89
90
91
92
93
94			`always@(posedge ckIn or posedge pwron_reset)`
95			`if( pwron_reset) reset_cnt <= 4'b1111;`
96			`else`
97			`if(\|reset_cnt) reset_cnt <= reset_cnt-4'b0001;`
98			`else reset_cnt <= 4'b0000;`
99
100
101
102			`always@(posedge ckIn or posedge pwron_reset)`
103			`if( pwron_reset) ref_reset <= 1'b1;`
104			`else ref_reset <= \|reset_cnt;`
105
106
107			`always@(posedge dll_clk)`
108			`if(dll_reset)`
109			`begin`
110			`one_usec <= 1'b0;`
111			`counter <= FREQ*PLL_MULT/2;`
112			`end`
113			`else if(counter == 7'b0000001)`
114			`begin`
115			`one_usec <= !one_usec;`
116			`counter <= FREQ*PLL_MULT/2;`
117			`end`
118			`else`
119			`begin`
120			`one_usec <= one_usec;`
121			`counter <= counter -7'b0000001;`
122			`end`
123
124
125
126			`cde_clock_dll`
127			`#(.MULT (PLL_MULT),`
128			`.DIV (PLL_DIV),`
129			`.SIZE (PLL_SIZE)`
130			`)`
131			`dll (`
132			`.ref_clk (ckIn),`
133			`.reset (pwron_reset),`
134			`.dll_clk_out (dll_clk),`
135			`.div_clk_out (div_clk_out)`
136			`);`
137
138
139
140			`cde_sync_with_reset`
141			`#(.WIDTH (1),`
142			`.DEPTH (2),`
143			`.RST_VAL(1'b1)`
144			`)`
145			`ref_rsync(`
146			`.clk (div_clk_out),`
147			`.reset_n (!pwron_reset),`
148			`.data_in (ref_reset),`
149			`.data_out (reset)`
150			`);`
151
152
153			`cde_sync_with_reset`
154			`#(.WIDTH (1),`
155			`.DEPTH (2),`
156			`.RST_VAL(1'b1)`
157			`)`
158			`dll_rsync(`
159			`.clk (dll_clk),`
160			`.reset_n (!pwron_reset),`
161			`.data_in (ref_reset),`
162			`.data_out (dll_reset)`
163			`);`
164
165
166
167			`endmodule`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_sys.v] - Blame information for rev 131