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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [syn/] [clock_dll.v] - Blame information for rev 131

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/**********************************************************************/
/*                                                                    */
/*                                                                    */
/*   Copyright (c) 2012 Ouabache Design Works                         */
/*                                                                    */
/*          All Rights Reserved Worldwide                             */
/*                                                                    */
/*   Licensed under the Apache License,Version2.0 (the'License');     */
/*   you may not use this file except in compliance with the License. */
/*   You may obtain a copy of the License at                          */
/*                                                                    */
/*       http://www.apache.org/licenses/LICENSE-2.0                   */
/*                                                                    */
/*   Unless required by applicable law or agreed to in                */
/*   writing, software distributed under the License is               */
/*   distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES              */
/*   OR CONDITIONS OF ANY KIND, either express or implied.            */
/*   See the License for the specific language governing              */
/*   permissions and limitations under the License.                   */
/**********************************************************************/
 
 
 
module
cde_clock_dll
#(parameter   DIV=4  ,
  parameter   MULT=2 ,
  parameter   SIZE=4
) (
input   wire        ref_clk,         // input clock
input   wire        reset,           // input reset
output  wire         dll_clk_out,     // output clock at higher frequency
output  wire         div_clk_out      // output clock at synthesized frequency
    );
 
 
assign dll_clk_out = ref_clk;
assign div_clk_out = ref_clk;
 
 
 
endmodule
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`/**********************************************************************/`
2			`/* */`
3			`/* */`
4			`/* Copyright (c) 2012 Ouabache Design Works */`
5			`/* */`
6			`/* All Rights Reserved Worldwide */`
7			`/* */`
8			`/* Licensed under the Apache License,Version2.0 (the'License'); */`
9			`/* you may not use this file except in compliance with the License. */`
10			`/* You may obtain a copy of the License at */`
11			`/* */`
12			`/* http://www.apache.org/licenses/LICENSE-2.0 */`
13			`/* */`
14			`/* Unless required by applicable law or agreed to in */`
15			`/* writing, software distributed under the License is */`
16			`/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */`
17			`/* OR CONDITIONS OF ANY KIND, either express or implied. */`
18			`/* See the License for the specific language governing */`
19			`/* permissions and limitations under the License. */`
20			`/**********************************************************************/`
21
22
23
24			`module`
25			`cde_clock_dll`
26			`#(parameter DIV=4 ,`
27			`parameter MULT=2 ,`
28			`parameter SIZE=4`
29			`) (`
30			`input wire ref_clk, // input clock`
31			`input wire reset, // input reset`
32			`output wire dll_clk_out, // output clock at higher frequency`
33			`output wire div_clk_out // output clock at synthesized frequency`
34			`);`
35
36
37			`assign dll_clk_out = ref_clk;`
38			`assign div_clk_out = ref_clk;`
39
40
41
42			`endmodule`
43
44

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [syn/] [clock_dll.v] - Blame information for rev 131