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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [syn/] [dll] - Blame information for rev 134

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always@(*)
begin
dll_clk_out = ref_clk;
end
 
 
always@(posedge ref_clk or posedge reset)
if(reset) div_clk_out <= 1'b0;
else      div_clk_out <= !div_clk_out;
 
 

Line No.	Rev	Author	Line
1	134	jt_eaton
2			`always@(*)`
3			`begin`
4			`dll_clk_out = ref_clk;`
5			`end`
6
7
8			`always@(posedge ref_clk or posedge reset)`
9			`if(reset) div_clk_out <= 1'b0;`
10			`else div_clk_out <= !div_clk_out;`
11
12

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [syn/] [dll] - Blame information for rev 134