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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_dll.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
clock
dll  default
 
 
 
 

 
 
 
 
 
 
 

 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../verilog/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

DIV4
MULT2
SIZE4

 

 
ref_clk
wire
in

 
 
dll_clk_out
wire
out

 
 
reset
wire
in

 
 
 
 
div_clk_out
reg
out

 
 
 

 

 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`clock`
15			`dll default`
16
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23
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26
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35			`fs-sim`
36
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39			`dest_dir`
40			`../verilog/sim/`
41			`verilogSourcelibraryDir`
42
43
44
45
46
47
48			`fs-syn`
49
50
51			`dest_dir`
52			`../verilog/syn/`
53			`verilogSourcelibraryDir`
54
55
56
57
58
59
60
61
62
63			`fs-lint`
64
65			`dest_dir../verilog/syn/`
66			`verilogSourcelibraryDir`
67
68
69
70
71
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73
74
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76
77
78
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87			`sim:Simulation:`
88
89			`Verilog`
90
91
92			`fs-sim`
93
94
95
96
97			`syn:Synthesis:`
98
99			`Verilog`
100
101
102			`fs-syn`
103
104
105
106
107			`doc`
108
109
110			`spirit:library="Testbench"`
111			`spirit:name="toolflow"`
112			`spirit:version="documentation"/>`
113
114			`:Documentation:`
115			`Verilog`
116
117
118
119
120
121
122
123
124
125			`DIV4`
126			`MULT2`
127			`SIZE4`
128
129
130
131
132			`ref_clk`
133			`wire`
134			`in`
135
136
137
138			`dll_clk_out`
139			`wire`
140			`out`
141
142
143
144			`reset`
145			`wire`
146			`in`
147
148
149
150
151
152			`div_clk_out`
153			`reg`
154			`out`
155
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_dll.xml] - Blame information for rev 131