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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_dll.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
clock
dll  default
 
 
 
 

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
  
    
      destination
      clock_dll
    
  

 
 

  gen_verilog_sim
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
  
    
      destination
      clock_dll
    
  

 
 
 
 

 
 
 
 
 
 
 
 
 
 
 

       
 
 
         
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
             
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

DIV4
MULT2
SIZE4

 

 
ref_clk
wire
in

 
 
reset
wire
in

 
dll_clk_out
reg
out

 
div_clk_out
reg
out

 
 
 

 

 
 
 
 
 

 
   
      fs-sim
 
    
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/timescale
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/dll
        verilogSourcefragment
      
 
      
        
        ../verilog/sim/clock_dll
        verilogSourcemodule
      
 
 
 
 
       
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
      
        
        ../verilog/syn/dll
        verilogSourcefragment
      
 
      
        
        ../verilog/syn/clock_dll
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_dll.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	134	jt_eaton
2	131	jt_eaton
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`clock`
15			`dll default`
16
17
18
19
20
21
22
23
24
25	134	jt_eaton
26			`gen_verilog_sim`
27			`104.0`
28			`none`
29			`:Simulation:`
30			`./tools/verilog/gen_verilog`
31
32
33			`destination`
34			`clock_dll`
35
36
37
38	131	jt_eaton
39
40	134	jt_eaton
41			`gen_verilog_sim`
42			`104.0`
43			`none`
44			`:Synthesis:`
45			`./tools/verilog/gen_verilog`
46
47
48			`destination`
49			`clock_dll`
50
51
52
53	131	jt_eaton
54
55
56
57	134	jt_eaton
58	131	jt_eaton
59
60
61
62
63
64
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66
67
68
69	134	jt_eaton
70
71	131	jt_eaton
72	134	jt_eaton
73
74			`verilog`
75
76
77			`spirit:library="Testbench"`
78			`spirit:name="toolflow"`
79			`spirit:version="verilog"/>`
80
81
82	131	jt_eaton
83
84
85
86	134	jt_eaton
87	131	jt_eaton	`sim:Simulation:`
88
89			`Verilog`
90
91
92			`fs-sim`
93
94
95
96
97			`syn:Synthesis:`
98
99			`Verilog`
100
101
102			`fs-syn`
103
104
105
106
107			`doc`
108
109
110			`spirit:library="Testbench"`
111			`spirit:name="toolflow"`
112			`spirit:version="documentation"/>`
113
114			`:Documentation:`
115			`Verilog`
116
117
118
119
120
121
122
123
124
125			`DIV4`
126			`MULT2`
127			`SIZE4`
128
129
130
131
132			`ref_clk`
133			`wire`
134			`in`
135
136
137
138			`reset`
139			`wire`
140			`in`
141
142
143	134	jt_eaton	`dll_clk_out`
144			`reg`
145			`out`
146
147	131	jt_eaton
148			`div_clk_out`
149			`reg`
150			`out`
151
152
153
154
155
156
157
158
159
160
161	134	jt_eaton
162
163
164
165
166			`fs-sim`
167
168
169
170			`../verilog/copyright`
171			`verilogSourceinclude`
172
173
174
175
176			`../verilog/timescale`
177			`verilogSourceinclude`
178
179
180
181
182			`../verilog/sim/dll`
183			`verilogSourcefragment`
184
185
186
187
188			`../verilog/sim/clock_dll`
189			`verilogSourcemodule`
190
191
192
193
194
195
196			`dest_dir`
197			`../views/sim/`
198			`verilogSourcelibraryDir`
199
200
201
202
203
204
205			`fs-syn`
206
207
208
209
210
211
212			`../verilog/copyright`
213			`verilogSourceinclude`
214
215
216
217
218
219
220			`../verilog/syn/dll`
221			`verilogSourcefragment`
222
223
224
225
226			`../verilog/syn/clock_dll`
227			`verilogSourcemodule`
228
229
230
231
232
233			`dest_dir`
234			`../views/syn/`
235			`verilogSourcelibraryDir`
236
237
238
239
240
241
242
243
244
245			`fs-lint`
246
247			`dest_dir../views/syn/`
248			`verilogSourcelibraryDir`
249
250
251
252
253
254
255
256
257
258
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260
261
262
263	131	jt_eaton