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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_gater.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
clock
gater
 
 
 

 
 clk_in
 
 
      
        
          
            
             clk
             clk_in
            
          
        
      
  
 
 
 
  clk_out
 
 
      
        
          
            
             clk
             clk_out
            
          
        
      
  
 
 
 
 enable
  
   
      
      
          
            
            enable
            enable
            
          
        
      
  
 
 

 
 
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      clock_gater
    
  

 
 
 
 
 

 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 

 
enable
wire
in

 
clk_in
wire
in

 
atg_clk_mode
wire
in

 
 
 
clk_out
wire
out

 
 
 
 
 

 

 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/clock_gater
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/common/clock_gater
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        
        ../verilog/common/clock_gater
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_gater.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`clock`
15			`gater`
16	131	jt_eaton
17
18
19	135	jt_eaton
20	131	jt_eaton
21	135	jt_eaton	`clk_in`
22
23
24
25
26
27
28			`clk`
29			`clk_in`
30
31
32
33
34
35
36	131	jt_eaton
37
38	135	jt_eaton	`clk_out`
39
40
41
42
43
44
45			`clk`
46			`clk_out`
47
48
49
50
51
52
53	131	jt_eaton
54
55	135	jt_eaton	`enable`
56
57
58
59
60
61
62			`enable`
63			`enable`
64
65
66
67
68
69
70	131	jt_eaton
71	135	jt_eaton
72	131	jt_eaton
73
74
75
76
77
78	135	jt_eaton
79	131	jt_eaton
80
81	135	jt_eaton
82			`gen_verilog`
83			`104.0`
84			`none`
85			`:common:`
86			`tools/verilog/gen_verilog`
87
88
89			`destination`
90			`clock_gater`
91
92
93
94	131	jt_eaton
95
96
97
98
99	135	jt_eaton
100	131	jt_eaton
101	135	jt_eaton
102
103
104
105
106
107
108
109
110			`verilog`
111
112
113			`ipxact:library="Testbench"`
114			`ipxact:name="toolflow"`
115			`ipxact:version="verilog"/>`
116
117
118
119
120
121
122			`common:common:`
123			`Verilog`
124
125
126			`fs-common`
127
128
129
130
131
132			`sim:Simulation:`
133	131	jt_eaton
134	135	jt_eaton	`Verilog`
135
136
137			`fs-sim`
138
139
140	131	jt_eaton
141	135	jt_eaton
142			`syn:Synthesis:`
143	131	jt_eaton
144	135	jt_eaton	`Verilog`
145
146
147			`fs-syn`
148
149
150	131	jt_eaton
151
152
153	135	jt_eaton
154			`doc`
155
156
157			`ipxact:library="Testbench"`
158			`ipxact:name="toolflow"`
159			`ipxact:version="documentation"/>`
160
161			`:Documentation:`
162			`Verilog`
163
164	131	jt_eaton
165
166	135	jt_eaton
167	131	jt_eaton
168
169
170
171	135	jt_eaton
172	131	jt_eaton
173	135	jt_eaton	`enable`
174			`wire`
175			`in`
176
177	131	jt_eaton
178	135	jt_eaton	`clk_in`
179			`wire`
180			`in`
181
182	131	jt_eaton
183	135	jt_eaton	`atg_clk_mode`
184			`wire`
185			`in`
186
187	131	jt_eaton
188
189
190	135	jt_eaton	`clk_out`
191			`wire`
192			`out`
193
194	131	jt_eaton
195
196
197
198
199	135	jt_eaton
200	131	jt_eaton
201	135	jt_eaton
202	131	jt_eaton
203
204
205
206
207	135	jt_eaton
208	131	jt_eaton
209	135	jt_eaton
210			`fs-common`
211	131	jt_eaton
212	135	jt_eaton
213
214			`../verilog/clock_gater`
215			`verilogSourcefragment`
216
217	131	jt_eaton
218
219	135	jt_eaton
220
221			`../verilog/copyright`
222			`verilogSourceinclude`
223
224	131	jt_eaton
225
226
227	135	jt_eaton
228	131	jt_eaton
229	134	jt_eaton
230	135	jt_eaton
231			`fs-sim`
232	134	jt_eaton
233	135	jt_eaton
234
235			`../verilog/common/clock_gater`
236			`verilogSourcemodule`
237
238	134	jt_eaton
239	135	jt_eaton
240			`dest_dir`
241			`../views/sim/`
242			`verilogSourcelibraryDir`
243
244	134	jt_eaton
245	135	jt_eaton
246	134	jt_eaton
247
248	135	jt_eaton
249			`fs-syn`
250	134	jt_eaton
251	135	jt_eaton
252
253			`../verilog/common/clock_gater`
254			`verilogSourcemodule`
255
256	134	jt_eaton
257	135	jt_eaton
258			`dest_dir`
259			`../views/syn/`
260			`verilogSourcelibraryDir`
261
262	134	jt_eaton
263
264
265	135	jt_eaton
266	134	jt_eaton
267
268	135	jt_eaton
269	134	jt_eaton
270	135	jt_eaton	`fs-lint`
271
272			`dest_dir../views/syn/`
273			`verilogSourcelibraryDir`
274
275	134	jt_eaton
276	135	jt_eaton
277	134	jt_eaton
278
279
280
281
282	135	jt_eaton
283	134	jt_eaton
284
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296	135	jt_eaton