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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_gater.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
clock
gater  default
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      clock_gater
    
  

 
 
 
 
 

 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 

 
enable
wire
in

 
clk_in
wire
in

 
atg_clk_mode
wire
in

 
 
 
clk_out
wire
out

 
 
 
 
 

 

 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/clock_gater
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/common/clock_gater
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        
        ../verilog/common/clock_gater
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_gater.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`clock`
15			`gater default`
16
17
18
19
20
21
22
23	134	jt_eaton
24			`gen_verilog`
25			`104.0`
26			`none`
27			`common`
28			`./tools/verilog/gen_verilog`
29
30
31			`destination`
32			`clock_gater`
33
34
35
36	131	jt_eaton
37
38
39
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41	134	jt_eaton
42	131	jt_eaton
43
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47	134	jt_eaton
48
49	131	jt_eaton
50
51	134	jt_eaton
52			`verilog`
53
54
55			`spirit:library="Testbench"`
56			`spirit:name="toolflow"`
57			`spirit:version="verilog"/>`
58
59
60	131	jt_eaton
61
62
63	134	jt_eaton
64			`commoncommon`
65			`Verilog`
66
67
68			`fs-common`
69
70
71	131	jt_eaton
72
73
74			`sim:Simulation:`
75
76			`Verilog`
77
78
79			`fs-sim`
80
81
82
83
84			`syn:Synthesis:`
85
86			`Verilog`
87
88
89			`fs-syn`
90
91
92
93
94
95
96			`doc`
97
98
99			`spirit:library="Testbench"`
100			`spirit:name="toolflow"`
101			`spirit:version="documentation"/>`
102
103			`:Documentation:`
104			`Verilog`
105
106
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111
112
113
114
115			`enable`
116			`wire`
117			`in`
118
119
120			`clk_in`
121			`wire`
122			`in`
123
124
125			`atg_clk_mode`
126			`wire`
127			`in`
128
129
130
131
132			`clk_out`
133			`wire`
134			`out`
135
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149	134	jt_eaton
150	131	jt_eaton
151	134	jt_eaton
152			`fs-common`
153	131	jt_eaton
154	134	jt_eaton
155
156			`../verilog/clock_gater`
157			`verilogSourcefragment`
158
159	131	jt_eaton
160
161	134	jt_eaton
162
163			`../verilog/copyright`
164			`verilogSourceinclude`
165
166	131	jt_eaton
167
168
169	134	jt_eaton
170	131	jt_eaton
171	134	jt_eaton
172
173			`fs-sim`
174
175
176
177			`../verilog/common/clock_gater`
178			`verilogSourcemodule`
179
180
181
182			`dest_dir`
183			`../views/sim/`
184			`verilogSourcelibraryDir`
185
186
187
188
189
190
191			`fs-syn`
192
193
194
195			`../verilog/common/clock_gater`
196			`verilogSourcemodule`
197
198
199
200			`dest_dir`
201			`../views/syn/`
202			`verilogSourcelibraryDir`
203
204
205
206
207
208
209
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211
212			`fs-lint`
213
214			`dest_dir../views/syn/`
215			`verilogSourcelibraryDir`
216
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238	131	jt_eaton