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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_sys.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
clock
sys  default
 
 
 

 
 
 
 
 
 
 
 

 
 

 
 clock
  
  
  
    
      
        clk
        div_clk_out
      
    
 
 
 
 reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="cde"
                                   spirit:name="clock"
                                   spirit:version="sys.design"/>
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
                            Verilog
              
                     
                            fs-syn
                     
              
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
 
 
      
 

FREQ48
PLL_MULT2
PLL_DIV4
PLL_SIZE4
CLOCK_SRC0
RESET_SENSE0

 

 
a_clk_pad_in
wire
in

 
b_clk_pad_in
wire
in

 
pwron_pad_in
wire
in

 
div_clk_out
reg
out

 
one_usec
reg
out

 
reset
wire
out

 
 

 

 
 
 
 
 
 

 
   
      fs-sim
 
 
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../verilog/
        verilogSource
        libraryDir
      
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir
        ../verilog/
        verilogSourcelibraryDir
      
    
 
 
 
 

 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_sys.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`clock`
15			`sys default`
16
17
18
19
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22
23
24
25
26
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30
31
32
33			`clock`
34
35
36
37
38
39			`clk`
40			`div_clk_out`
41
42
43
44
45
46			`reset`
47
48
49
50
51
52			`reset`
53			`reset`
54
55
56
57
58
59
60
61
62
63
64
65
66
67			`Hierarchical`
68
69
70			`spirit:library="cde"`
71			`spirit:name="clock"`
72			`spirit:version="sys.design"/>`
73
74
75
76			`sim:Simulation:`
77			`Verilog`
78
79
80			`fs-sim`
81
82
83
84
85			`syn:Synthesis:`
86			`Verilog`
87
88
89			`fs-syn`
90
91
92
93
94			`doc`
95
96
97			`spirit:library="Testbench"`
98			`spirit:name="toolflow"`
99			`spirit:version="documentation"/>`
100
101			`:Documentation:`
102			`Verilog`
103
104
105
106
107
108
109
110
111
112
113
114
115			`FREQ48`
116			`PLL_MULT2`
117			`PLL_DIV4`
118			`PLL_SIZE4`
119			`CLOCK_SRC0`
120			`RESET_SENSE0`
121
122
123
124
125			`a_clk_pad_in`
126			`wire`
127			`in`
128
129
130			`b_clk_pad_in`
131			`wire`
132			`in`
133
134
135			`pwron_pad_in`
136			`wire`
137			`in`
138
139
140			`div_clk_out`
141			`reg`
142			`out`
143
144
145			`one_usec`
146			`reg`
147			`out`
148
149
150			`reset`
151			`wire`
152			`out`
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168			`fs-sim`
169
170
171
172			`dest_dir`
173			`../verilog/`
174			`verilogSource`
175			`libraryDir`
176
177
178
179
180
181
182			`fs-syn`
183
184
185			`dest_dir`
186			`../verilog/`
187			`verilogSource`
188			`libraryDir`
189
190
191
192
193
194
195
196
197			`fs-lint`
198
199			`dest_dir`
200			`../verilog/`
201			`verilogSourcelibraryDir`
202
203
204
205
206
207
208
209
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212