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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_sys.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
clock
sys  default
 
 
 
 

 
 clock
  
  
  
    
      
        clk
        div_clk_out
      
    
 
 
 
 reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      clock_sys
    
  

 
 
 
 
 
 
 

 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="cde"
                                   spirit:name="clock"
                                   spirit:version="sys.design"/>
              
 
            
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
                            Verilog
              
                     
                            fs-syn
                     
              
 
             
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
 
 
      
 

FREQ48
PLL_MULT2
PLL_DIV4
PLL_SIZE4
CLOCK_SRC0
RESET_SENSE0

 

 
a_clk_pad_in
wire
in

 
b_clk_pad_in
wire
in

 
pwron_pad_in
wire
in

 
div_clk_out
wire
out

 
one_usec
reg
out

 
reset
wire
out

 
 

 

 
 
 
 
 
 

 
 
 
 
 
   
      fs-common
 
      
        
        ../verilog/clock_sys
        verilogSourcefragment
      
 
   
 
 
  
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/clock_sys
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSource
        libraryDir
      
 
  
 
 
   
      fs-syn
 
 
     
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/clock_sys
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
    
 
 
 
 

 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_sys.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`clock`
15			`sys default`
16
17
18
19
20
21
22			`clock`
23
24
25
26
27
28			`clk`
29			`div_clk_out`
30
31
32
33
34
35			`reset`
36
37
38
39
40
41			`reset`
42			`reset`
43
44
45
46
47
48
49
50	134	jt_eaton
51	131	jt_eaton
52
53	134	jt_eaton
54			`gen_verilog`
55			`104.0`
56			`none`
57			`common`
58			`./tools/verilog/gen_verilog`
59
60
61			`destination`
62			`clock_sys`
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78	131	jt_eaton
79
80
81
82			`Hierarchical`
83
84
85			`spirit:library="cde"`
86			`spirit:name="clock"`
87			`spirit:version="sys.design"/>`
88
89
90	134	jt_eaton
91			`verilog`
92
93
94			`spirit:library="Testbench"`
95			`spirit:name="toolflow"`
96			`spirit:version="verilog"/>`
97
98
99
100
101
102	131	jt_eaton
103	134	jt_eaton	`commoncommon`
104			`Verilog`
105
106
107			`fs-common`
108
109
110
111
112
113
114
115	131	jt_eaton	`sim:Simulation:`
116			`Verilog`
117
118
119			`fs-sim`
120
121
122
123
124			`syn:Synthesis:`
125			`Verilog`
126
127
128			`fs-syn`
129
130
131
132
133			`doc`
134
135
136			`spirit:library="Testbench"`
137			`spirit:name="toolflow"`
138			`spirit:version="documentation"/>`
139
140			`:Documentation:`
141			`Verilog`
142
143
144
145
146
147
148
149
150
151
152
153
154			`FREQ48`
155			`PLL_MULT2`
156			`PLL_DIV4`
157			`PLL_SIZE4`
158			`CLOCK_SRC0`
159			`RESET_SENSE0`
160
161
162
163
164			`a_clk_pad_in`
165			`wire`
166			`in`
167
168
169			`b_clk_pad_in`
170			`wire`
171			`in`
172
173
174			`pwron_pad_in`
175			`wire`
176			`in`
177
178
179			`div_clk_out`
180	134	jt_eaton	`wire`
181	131	jt_eaton	`out`
182
183
184			`one_usec`
185			`reg`
186			`out`
187
188
189			`reset`
190			`wire`
191			`out`
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206	134	jt_eaton
207
208
209
210	131	jt_eaton
211	134	jt_eaton	`fs-common`
212
213
214
215			`../verilog/clock_sys`
216			`verilogSourcefragment`
217
218
219
220
221
222
223	131	jt_eaton	`fs-sim`
224
225
226	134	jt_eaton
227			`../verilog/copyright`
228			`verilogSourceinclude`
229
230
231
232
233
234			`../verilog/common/clock_sys`
235			`verilogSourcemodule`
236
237
238
239
240	131	jt_eaton	`dest_dir`
241	134	jt_eaton	`../views/sim/`
242	131	jt_eaton	`verilogSource`
243			`libraryDir`
244
245
246
247
248
249
250			`fs-syn`
251
252	134	jt_eaton
253
254
255			`../verilog/copyright`
256			`verilogSourceinclude`
257
258
259
260	131	jt_eaton
261	134	jt_eaton
262			`../verilog/common/clock_sys`
263			`verilogSourcemodule`
264
265
266
267
268	131	jt_eaton	`dest_dir`
269	134	jt_eaton	`../views/syn/`
270	131	jt_eaton	`verilogSource`
271			`libraryDir`
272
273
274
275
276
277
278
279
280			`fs-lint`
281
282			`dest_dir`
283	134	jt_eaton	`../views/syn/`
284	131	jt_eaton	`verilogSourcelibraryDir`
285
286
287
288
289
290
291
292
293
294
295