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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_sys.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
clock
sys
 
 
 
 

 
 clock
 
 
      
        
          
            
             clk
             div_clk_out
            
          
        
      
  
 
 
 
 reset
  
   
      
      
          
            
            reset
            reset
            
          
        
      
  
 
 

 
 

 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      clock_sys
    
  

 
 
 
 
 
 
 

 
 
 
 

 
        
        
        Hierarchical
        
        
        
 
 
 
 
 
  
 
              
              Hierarchical
              Hierarchical
              
 
            
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
                            Verilog
              
                     
                            fs-syn
                     
              
 
             
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
 
 
      
 

FREQ48
PLL_MULT2
PLL_DIV4
PLL_SIZE4
CLOCK_SRC0
RESET_SENSE0

 

 
a_clk_pad_in
wire
in

 
b_clk_pad_in
wire
in

 
pwron_pad_in
wire
in

 
div_clk_out
wire
out

 
one_usec
reg
out

 
reset
wire
out

 
 

 

 
 
 
 
 
 

 
 
 
 
 
   
      fs-common
 
      
        
        ../verilog/clock_sys
        verilogSourcefragment
      
 
   
 
 
  
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/clock_sys
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSource
        libraryDir
      
 
  
 
 
   
      fs-syn
 
 
     
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/clock_sys
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
    
 
 
 
 

 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_sys.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`clock`
15			`sys`
16	131	jt_eaton
17
18
19
20	135	jt_eaton
21	131	jt_eaton
22	135	jt_eaton	`clock`
23
24
25
26
27
28
29			`clk`
30			`div_clk_out`
31
32
33
34
35
36
37	131	jt_eaton
38
39	135	jt_eaton	`reset`
40
41
42
43
44
45
46			`reset`
47			`reset`
48
49
50
51
52
53
54	131	jt_eaton
55	135	jt_eaton
56	131	jt_eaton
57
58	135	jt_eaton
59	131	jt_eaton
60
61	135	jt_eaton
62			`gen_verilog`
63			`104.0`
64			`none`
65			`:common:`
66			`tools/verilog/gen_verilog`
67
68
69			`destination`
70			`clock_sys`
71
72
73
74	134	jt_eaton
75
76
77
78
79
80
81	135	jt_eaton
82	134	jt_eaton
83
84
85
86	135	jt_eaton
87	131	jt_eaton
88	135	jt_eaton
89
90			`Hierarchical`
91
92
93
94	131	jt_eaton
95	134	jt_eaton
96
97
98
99	135	jt_eaton
100	134	jt_eaton
101	135	jt_eaton
102			`Hierarchical`
103			`Hierarchical`
104
105	134	jt_eaton
106	135	jt_eaton
107			`verilog`
108
109
110			`ipxact:library="Testbench"`
111			`ipxact:name="toolflow"`
112			`ipxact:version="verilog"/>`
113
114
115	134	jt_eaton
116	131	jt_eaton
117
118	135	jt_eaton
119			`common:common:`
120			`Verilog`
121
122
123			`fs-common`
124
125
126	131	jt_eaton
127
128
129
130	135	jt_eaton
131			`sim:Simulation:`
132			`Verilog`
133
134
135			`fs-sim`
136
137
138	131	jt_eaton
139	135	jt_eaton
140			`syn:Synthesis:`
141			`Verilog`
142
143
144			`fs-syn`
145
146
147	131	jt_eaton
148	135	jt_eaton
149			`doc`
150
151
152			`ipxact:library="Testbench"`
153			`ipxact:name="toolflow"`
154			`ipxact:version="documentation"/>`
155
156			`:Documentation:`
157			`Verilog`
158
159	131	jt_eaton
160
161
162
163
164
165
166
167	135	jt_eaton
168	131	jt_eaton
169	135	jt_eaton
170			`FREQ48`
171			`PLL_MULT2`
172			`PLL_DIV4`
173			`PLL_SIZE4`
174			`CLOCK_SRC0`
175			`RESET_SENSE0`
176
177	131	jt_eaton
178	135	jt_eaton
179	131	jt_eaton
180	135	jt_eaton	`a_clk_pad_in`
181			`wire`
182			`in`
183
184	131	jt_eaton
185	135	jt_eaton	`b_clk_pad_in`
186			`wire`
187			`in`
188
189	131	jt_eaton
190	135	jt_eaton	`pwron_pad_in`
191			`wire`
192			`in`
193
194	131	jt_eaton
195	135	jt_eaton	`div_clk_out`
196			`wire`
197			`out`
198
199	131	jt_eaton
200	135	jt_eaton	`one_usec`
201			`reg`
202			`out`
203
204	131	jt_eaton
205	135	jt_eaton	`reset`
206			`wire`
207			`out`
208
209	131	jt_eaton
210
211	135	jt_eaton
212	131	jt_eaton
213	135	jt_eaton
214	131	jt_eaton
215	135	jt_eaton
216
217
218
219
220
221
222	134	jt_eaton
223
224
225
226	135	jt_eaton
227			`fs-common`
228	134	jt_eaton
229	135	jt_eaton
230
231			`../verilog/clock_sys`
232			`verilogSourcefragment`
233
234	134	jt_eaton
235	135	jt_eaton
236	134	jt_eaton
237
238	135	jt_eaton
239			`fs-sim`
240	131	jt_eaton
241	135	jt_eaton
242
243			`../verilog/copyright`
244			`verilogSourceinclude`
245
246	134	jt_eaton
247
248	135	jt_eaton
249
250			`../verilog/common/clock_sys`
251			`verilogSourcemodule`
252
253	134	jt_eaton
254
255	135	jt_eaton
256			`dest_dir`
257			`../views/sim/`
258			`verilogSource`
259			`libraryDir`
260
261	131	jt_eaton
262	135	jt_eaton
263	131	jt_eaton
264
265	135	jt_eaton
266			`fs-syn`
267	131	jt_eaton
268	134	jt_eaton
269	135	jt_eaton
270
271			`../verilog/copyright`
272			`verilogSourceinclude`
273
274	134	jt_eaton
275
276	135	jt_eaton
277
278			`../verilog/common/clock_sys`
279			`verilogSourcemodule`
280
281	134	jt_eaton
282
283	135	jt_eaton
284			`dest_dir`
285			`../views/syn/`
286			`verilogSource`
287			`libraryDir`
288
289	131	jt_eaton
290	135	jt_eaton
291	131	jt_eaton
292
293
294	135	jt_eaton
295	131	jt_eaton
296	135	jt_eaton	`fs-lint`
297
298			`dest_dir`
299			`../views/syn/`
300			`verilogSourcelibraryDir`
301
302
303	131	jt_eaton
304
305
306
307	135	jt_eaton
308	131	jt_eaton
309
310
311	135	jt_eaton