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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [divider/] [rtl/] [verilog/] [divider_def] - Blame information for rev 134

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reg  [SIZE-1:0]        divide_cnt;
 
always@(posedge clk)
  if(reset)            divider_out    <= RESET;
  else
  if(!enable)          divider_out    <= 1'b0;
  else                 divider_out    <=  ( divide_cnt == SAMPLE );
 
always@(posedge clk)
  if(reset)            divide_cnt    <= divider_in;
  else
  if(!enable)          divide_cnt    <= divide_cnt;
  else
  if(!(|divide_cnt))   divide_cnt    <= divider_in;
  else                 divide_cnt    <= divide_cnt - 'b1;
 
 
 
 

Line No.	Rev	Author	Line
1	134	jt_eaton	`reg [SIZE-1:0] divide_cnt;`
2
3			`always@(posedge clk)`
4			`if(reset) divider_out <= RESET;`
5			`else`
6			`if(!enable) divider_out <= 1'b0;`
7			`else divider_out <= ( divide_cnt == SAMPLE );`
8
9			`always@(posedge clk)`
10			`if(reset) divide_cnt <= divider_in;`
11			`else`
12			`if(!enable) divide_cnt <= divide_cnt;`
13			`else`
14			`if(!(\|divide_cnt)) divide_cnt <= divider_in;`
15			`else divide_cnt <= divide_cnt - 'b1;`
16
17
18
19

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [divider/] [rtl/] [verilog/] [divider_def] - Blame information for rev 134