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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [divider/] [rtl/] [xml/] [cde_divider_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
divider
def  default
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      divider_def
    
  

 
 
 
 
 

 
 
 
 
 

       
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
          
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 

SIZE4
SAMPLE0
RESET1

 

 
clk
wire
in

 
reset
wire
in

 
 
enable
wire
in

 
 
 
 
divider_in
wire
in
SIZE-10

 
 
divider_out
reg
out

 
 

 

 
 
 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/divider_def
        verilogSourcefragment
      
 
    
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/divider_def
        verilogSourcemodule
      
 
       
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
     
        
        ../verilog/common/divider_def
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
   
 
 
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [divider/] [rtl/] [xml/] [cde_divider_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`divider`
15			`def default`
16
17
18
19
20
21
22
23
24
25	134	jt_eaton
26			`gen_verilog`
27			`104.0`
28			`none`
29			`common`
30			`./tools/verilog/gen_verilog`
31
32
33			`destination`
34			`divider_def`
35
36
37
38	131	jt_eaton
39
40
41
42
43	134	jt_eaton
44	131	jt_eaton
45
46
47
48
49
50
51	134	jt_eaton
52			`verilog`
53
54
55			`spirit:library="Testbench"`
56			`spirit:name="toolflow"`
57			`spirit:version="verilog"/>`
58
59
60	131	jt_eaton
61
62
63
64	134	jt_eaton	`commoncommon`
65			`Verilog`
66
67
68			`fs-common`
69
70
71
72
73
74	131	jt_eaton	`sim:Simulation:`
75			`Verilog`
76
77
78			`fs-sim`
79
80
81
82
83			`syn:Synthesis:`
84			`Verilog`
85
86
87			`fs-syn`
88
89
90
91
92
93			`doc`
94
95
96			`spirit:library="Testbench"`
97			`spirit:name="toolflow"`
98			`spirit:version="documentation"/>`
99
100			`:Documentation:`
101			`Verilog`
102
103
104
105
106
107
108
109
110
111			`SIZE4`
112			`SAMPLE0`
113			`RESET1`
114
115
116
117
118			`clk`
119			`wire`
120			`in`
121
122
123			`reset`
124			`wire`
125			`in`
126
127
128
129			`enable`
130			`wire`
131			`in`
132
133
134
135
136
137			`divider_in`
138			`wire`
139			`in`
140			`SIZE-10`
141
142
143
144			`divider_out`
145			`reg`
146			`out`
147
148
149
150
151
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155
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159
160	134	jt_eaton
161	131	jt_eaton
162	134	jt_eaton
163			`fs-common`
164	131	jt_eaton
165	134	jt_eaton
166
167			`../verilog/divider_def`
168			`verilogSourcefragment`
169
170	131	jt_eaton
171	134	jt_eaton
172	131	jt_eaton
173	134	jt_eaton
174
175			`fs-sim`
176
177
178
179			`../verilog/copyright`
180			`verilogSourceinclude`
181
182
183
184
185
186			`../verilog/common/divider_def`
187			`verilogSourcemodule`
188
189
190
191			`dest_dir`
192			`../views/sim/`
193			`verilogSourcelibraryDir`
194
195
196
197
198
199
200			`fs-syn`
201
202
203
204			`../verilog/copyright`
205			`verilogSourceinclude`
206
207
208
209
210			`../verilog/common/divider_def`
211			`verilogSourcemodule`
212
213
214
215			`dest_dir`
216			`../views/syn/`
217			`verilogSourcelibraryDir`
218
219
220
221
222
223
224
225
226
227			`fs-lint`
228
229			`dest_dir`
230			`../views/syn/`
231			`verilogSourcelibraryDir`
232
233
234
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248	131	jt_eaton