Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

cde

fifo

def

  gen_verilog

  104.0

  none

  :*common:*

  tools/verilog/gen_verilog

      destination

      fifo_def

                                Hierarchical

                                verilog

                                verilog

                                cde_fifo_def

                                                WIDTH

                                                8

                                        fs-sim

        rtl

        verilog:Kactus2:

        verilog

              Hierarchical

               Hierarchical

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              common:*common:*

              Verilog

                            fs-common

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

WIDTH8

SIZE2

WORDS4

clk

wire

in

reset

wire

in

push

wire

in

pop

wire

in

din

wire

in

WIDTH-10

dout

wire

out

WIDTH-10

full

reg

out

empty

reg

out

over_run

reg

out

under_run

reg

out

      fs-common

        ../verilog/fifo_def

        verilogSourcefragment

        ../verilog/copyright.v

        verilogSourceinclude

      fs-sim

        ../verilog/common/fifo_def

        verilogSourcemodule

       dest_dir

        ../views/sim/

        verilogSourcelibraryDir

      fs-syn

        dest_dir

        ../views/sim/

        verilogSourcelibraryDir

      fs-lint

        dest_dir../views/sim/

        verilogSourcelibraryDir