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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [fifo/] [rtl/] [xml/] [cde_fifo_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
fifo
def  default
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      fifo_def
    
  

 
 
 
 
 
 

 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="cde"
                                   spirit:name="fifo"
                                   spirit:version="def.design"/>
              
 
             
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
             
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
 
 
        
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
      
 
 

 
   
      fs-common
 
      
        
        ../verilog/fifo_def
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
 
 
   
 
 
 
   
      fs-sim
 
    
        
        ../verilog/common/fifo_def
        verilogSourcemodule
      
 
 
 
      
       dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
   
 
    
 
      fs-lint
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 

WIDTH8
SIZE2
WORDS4

 
 

 
clk
wire
in

 
reset
wire
in

 
push
wire
in

 
pop
wire
in

 
 
 
 
din
wire
in
WIDTH-10

 
 
dout
wire
out
WIDTH-10

 
 
full
reg
out

 
empty
reg
out

 
over_run
reg
out

 
under_run
reg
out

 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [fifo/] [rtl/] [xml/] [cde_fifo_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`fifo`
15			`def default`
16
17
18
19
20
21
22
23	134	jt_eaton
24			`gen_verilog`
25			`104.0`
26			`none`
27			`common`
28			`./tools/verilog/gen_verilog`
29
30
31			`destination`
32			`fifo_def`
33
34
35
36	131	jt_eaton
37
38
39
40
41
42	134	jt_eaton
43	131	jt_eaton
44
45
46
47
48
49
50
51
52
53			`Hierarchical`
54
55
56			`spirit:library="cde"`
57			`spirit:name="fifo"`
58			`spirit:version="def.design"/>`
59
60
61	134	jt_eaton
62			`verilog`
63
64
65			`spirit:library="Testbench"`
66			`spirit:name="toolflow"`
67			`spirit:version="verilog"/>`
68
69
70
71
72			`commoncommon`
73			`Verilog`
74
75
76			`fs-common`
77
78
79
80
81
82
83	131	jt_eaton
84			`sim:Simulation:`
85			`Verilog`
86
87
88			`fs-sim`
89
90
91
92
93			`syn:Synthesis:`
94			`Verilog`
95
96
97			`fs-syn`
98
99
100
101	134	jt_eaton
102	131	jt_eaton
103
104
105
106			`doc`
107
108
109			`spirit:library="Testbench"`
110			`spirit:name="toolflow"`
111			`spirit:version="documentation"/>`
112
113			`:Documentation:`
114			`Verilog`
115
116
117
118
119
120
121
122
123
124	134	jt_eaton
125	131	jt_eaton
126	134	jt_eaton
127			`fs-common`
128
129
130
131			`../verilog/fifo_def`
132			`verilogSourcefragment`
133
134
135
136
137
138			`../verilog/copyright`
139			`verilogSourceinclude`
140
141
142
143
144
145
146
147
148
149			`fs-sim`
150
151
152
153			`../verilog/common/fifo_def`
154			`verilogSourcemodule`
155
156
157
158
159
160			`dest_dir`
161			`../views/sim/`
162			`verilogSourcelibraryDir`
163
164
165
166
167
168
169			`fs-syn`
170
171
172			`dest_dir`
173			`../views/sim/`
174			`verilogSourcelibraryDir`
175
176
177
178
179
180
181
182
183			`fs-lint`
184
185			`dest_dir../views/sim/`
186			`verilogSourcelibraryDir`
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201	131	jt_eaton
202			`WIDTH8`
203			`SIZE2`
204			`WORDS4`
205
206
207
208
209
210			`clk`
211			`wire`
212			`in`
213
214
215			`reset`
216			`wire`
217			`in`
218
219
220			`push`
221			`wire`
222			`in`
223
224
225			`pop`
226			`wire`
227			`in`
228
229
230
231
232
233			`din`
234			`wire`
235			`in`
236			`WIDTH-10`
237
238
239
240			`dout`
241	134	jt_eaton	`wire`
242	131	jt_eaton	`out`
243			`WIDTH-10`
244
245
246
247			`full`
248			`reg`
249			`out`
250
251
252			`empty`
253			`reg`
254			`out`
255
256
257			`over_run`
258			`reg`
259			`out`
260
261
262			`under_run`
263			`reg`
264			`out`
265
266
267
268
269
270
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279