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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [fifo/] [sim/] [testbenches/] [xml/] [cde_fifo_def_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
cde
fifo
def_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      fifo_def_tb
    
  

 
 
 

 
 
 
 
 
 
 



 
       
 
              
              Params
              
              
                                   spirit:library="cde"
                                   spirit:name="fifo"
                                   spirit:version="def_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="cde"
                                   spirit:name="fifo"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
   
      fs-common
 
 
   
 
 
   
      fs-sim
 
 
 
      
        
        ../verilog/common/fifo_def_tb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/fifo_def_tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


Line No.	Rev	Author	Line
1	134	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`fifo`
15			`def_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33			`fifo_def_tb`
34
35
36
37
38
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45
46
47
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55			`Params`
56
57
58			`spirit:library="cde"`
59			`spirit:name="fifo"`
60			`spirit:version="def_dut.params"/>`
61
62
63
64
65
66			`Bfm`
67
68			`spirit:library="cde"`
69			`spirit:name="fifo"`
70			`spirit:version="bfm.design"/>`
71
72
73
74
75			`icarus`
76
77
78			`spirit:library="Testbench"`
79			`spirit:name="toolflow"`
80			`spirit:version="icarus"/>`
81
82
83
84
85
86
87
88			`commoncommon`
89			`Verilog`
90
91
92			`fs-common`
93
94
95
96
97
98			`sim:Simulation:`
99			`Verilog`
100
101
102			`fs-sim`
103
104
105
106
107			`lint:Lint:`
108			`Verilog`
109
110
111			`fs-lint`
112
113
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117
118
119
120
121
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130			`fs-common`
131
132
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134
135
136
137			`fs-sim`
138
139
140
141
142
143			`../verilog/common/fifo_def_tb`
144			`verilogSourcemodule`
145
146
147
148
149
150
151
152			`fs-lint`
153
154
155			`../verilog/common/fifo_def_tb`
156			`verilogSourcemodule`
157
158
159
160
161
162
163
164
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172

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [fifo/] [sim/] [testbenches/] [xml/] [cde_fifo_def_tb.xml] - Blame information for rev 134