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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [gates/] [rtl/] [xml/] [cde_gates_xor.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
gates
xor
 
 

 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      gates_xor
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      gates_xor
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 

 
 

 
 
 
 
 
 
 
 

refdes
U?
300
900
5
10
1
1
2

 

module_name
cde_gates_xor
400
0
5
10
0
1
2

 

vendor
opencores.org
0
-200
0
10
0
0
0

 

library
cde
0
-300
0
10
0
0
0

 
 

component
gates
0
-400
0
10
0
0
0

 
 
 

version
xor
0
-500
0
10
0
0
0

 
 
 
 
 
 
 
 

 

cde_gates_xor
 
 

 geda-project.org
 symbols
 gates
 def
 xor
 0
 100

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 200
 IN1
0

 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 600
 IN0
0

 
 
 

 geda-project.org
 symbols
 pins
 def
 out_wire
 1000
 400
 OUT
0

 
 

 
 
 
 
 

 
 


 
 
 
 
 
 

 
   
      fs-sim
 
       
        ../verilog/xor
        verilogSourcefragment
      
 
 
      
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        ../verilog/sim/gates_xor
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
       
        ../verilog/xor
        verilogSourcefragment
      
 
 
      
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        ../verilog/sim/gates_xor
        verilogSourcemodule
      
 
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
            
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 
 

 
IN0
wire
in

 
IN1
wire
in

 
 
 
OUT
wire
out

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [gates/] [rtl/] [xml/] [cde_gates_xor.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
5
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`gates`
15			`xor`
16
17
18
19
20
21
22			`gen_verilog_sim`
23			`104.0`
24			`none`
25			`:Simulation:`
26			`tools/verilog/gen_verilog`
27
28
29			`destination`
30			`gates_xor`
31
32
33
34
35
36
37			`gen_verilog_syn`
38			`104.0`
39			`none`
40			`:Synthesis:`
41			`tools/verilog/gen_verilog`
42
43
44			`destination`
45			`gates_xor`
46
47
48
49
50
51
52
53
54			`gen_verilogLib_sim`
55			`105.0`
56			`none`
57			`:Simulation:`
58			`tools/verilog/gen_verilogLib`
59
60
61			`dest_dir`
62			`../views`
63
64
65			`view`
66			`sim`
67
68
69
70
71
72
73
74			`gen_verilogLib_syn`
75			`105.0`
76			`none`
77			`:Synthesis:`
78			`tools/verilog/gen_verilogLib`
79
80
81			`dest_dir`
82			`../views`
83
84
85			`view`
86			`syn`
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108			`refdes`
109			`U?`
110			`300`
111			`900`
112			`5`
113			`10`
114			`1`
115			`1`
116			`2`
117
118
119
120			`module_name`
121			`cde_gates_xor`
122			`400`
123			`0`
124			`5`
125			`10`
126			`0`
127			`1`
128			`2`
129
130
131
132			`vendor`
133			`opencores.org`
134			`0`
135			`-200`
136			`0`
137			`10`
138			`0`
139			`0`
140			`0`
141
142
143
144			`library`
145			`cde`
146			`0`
147			`-300`
148			`0`
149			`10`
150			`0`
151			`0`
152			`0`
153
154
155
156
157			`component`
158			`gates`
159			`0`
160			`-400`
161			`0`
162			`10`
163			`0`
164			`0`
165			`0`
166
167
168
169
170
171			`version`
172			`xor`
173			`0`
174			`-500`
175			`0`
176			`10`
177			`0`
178			`0`
179			`0`
180
181
182
183
184
185
186
187
188
189
190
191
192			`cde_gates_xor`
193
194
195
196			`geda-project.org`
197			`symbols`
198			`gates`
199			`def`
200			`xor`
201			`0`
202			`100`
203
204
205
206
207
208
209			`geda-project.org`
210			`symbols`
211			`pins`
212			`def`
213			`in_wire`
214			`0`
215			`200`
216			`IN1`
217			`0`
218
219
220
221
222			`geda-project.org`
223			`symbols`
224			`pins`
225			`def`
226			`in_wire`
227			`0`
228			`600`
229			`IN0`
230			`0`
231
232
233
234
235
236			`geda-project.org`
237			`symbols`
238			`pins`
239			`def`
240			`out_wire`
241			`1000`
242			`400`
243			`OUT`
244			`0`
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268			`fs-sim`
269
270
271			`../verilog/xor`
272			`verilogSourcefragment`
273
274
275
276
277			`../verilog/copyright`
278			`verilogSourceinclude`
279
280
281
282
283			`../verilog/sim/gates_xor`
284			`verilogSourcemodule`
285
286
287
288
289
290			`dest_dir`
291			`../views/sim/`
292			`verilogSourcelibraryDir`
293
294
295
296
297
298
299			`fs-syn`
300
301
302
303			`../verilog/xor`
304			`verilogSourcefragment`
305
306
307
308
309			`../verilog/copyright`
310			`verilogSourceinclude`
311
312
313
314
315			`../verilog/sim/gates_xor`
316			`verilogSourcemodule`
317
318
319
320
321
322
323			`dest_dir`
324			`../views/syn/`
325			`verilogSourcelibraryDir`
326
327
328
329
330
331
332
333
334
335			`fs-lint`
336
337			`dest_dir`
338			`../views/syn/`
339			`verilogSourcelibraryDir`
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361			`sim:Simulation:`
362			`Verilog`
363
364
365			`fs-sim`
366
367
368
369
370			`syn:Synthesis:`
371			`Verilog`
372
373
374			`fs-syn`
375
376
377
378
379
380			`doc`
381
382
383			`ipxact:library="Testbench"`
384			`ipxact:name="toolflow"`
385			`ipxact:version="documentation"/>`
386
387			`:Documentation:`
388			`Verilog`
389
390
391
392
393
394
395
396
397
398
399
400
401			`IN0`
402			`wire`
403			`in`
404
405
406			`IN1`
407			`wire`
408			`in`
409
410
411
412
413			`OUT`
414			`wire`
415			`out`
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
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438