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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [doc/] [sch/] [cde_jtag_classic_sync.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 2100 300 1 0 0 in_port.sym
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{
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T 2100 300 5 10 1 1 0 6 1 1
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refdes=update_dr_clk
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}
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C 2100 700 1 0 0 in_port.sym
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{
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T 2100 700 5 10 1 1 0 6 1 1
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refdes=test_logic_reset
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}
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C 2100 1100 1 0 0 in_port.sym
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{
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T 2100 1100 5 10 1 1 0 6 1 1
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refdes=tdi
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}
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C 2100 1500 1 0 0 in_port.sym
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{
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T 2100 1500 5 10 1 1 0 6 1 1
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refdes=syn_tdo_i
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}
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C 2100 1900 1 0 0 in_port.sym
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{
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T 2100 1900 5 10 1 1 0 6 1 1
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refdes=shiftcapture_dr_clk
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}
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C 2100 2300 1 0 0 in_port.sym
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{
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T 2100 2300 5 10 1 1 0 6 1 1
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refdes=shift_dr
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}
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C 2100 2700 1 0 0 in_port.sym
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{
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T 2100 2700 5 10 1 1 0 6 1 1
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refdes=select
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}
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C 2100 3100 1 0 0 in_port.sym
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{
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T 2100 3100 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 2100 3500 1 0 0 in_port.sym
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{
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T 2100 3500 5 10 1 1 0 6 1 1
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refdes=capture_dr
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}
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C 4800 300  1 0 0 out_port.sym
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{
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T 5800 300 5  10 1 1 0 0 1 1
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refdes=tdo
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}
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C 4800 700  1 0 0 out_port.sym
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{
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T 5800 700 5  10 1 1 0 0 1 1
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refdes=syn_update_dr
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}
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C 4800 1100  1 0 0 out_port.sym
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{
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T 5800 1100 5  10 1 1 0 0 1 1
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refdes=syn_tdi_o
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}
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C 4800 1500  1 0 0 out_port.sym
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{
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T 5800 1500 5  10 1 1 0 0 1 1
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refdes=syn_shift_dr
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}
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C 4800 1900  1 0 0 out_port.sym
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{
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T 5800 1900 5  10 1 1 0 0 1 1
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refdes=syn_select
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}
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C 4800 2300  1 0 0 out_port.sym
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{
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T 5800 2300 5  10 1 1 0 0 1 1
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refdes=syn_reset
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}
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C 4800 2700  1 0 0 out_port.sym
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{
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T 5800 2700 5  10 1 1 0 0 1 1
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refdes=syn_clk
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}
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C 4800 3100  1 0 0 out_port.sym
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{
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T 5800 3100 5  10 1 1 0 0 1 1
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refdes=syn_capture_dr
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}

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