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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [doc/] [sch/] [cde_jtag_tap_logic.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
C 2000 300 1 0 0 in_port_vector.sym
3 
{
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T 2000 300 5 10 1 1 0 6 1 1
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refdes=instruction[3:0]
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}
7 
C 2000 700 1 0 0 in_port.sym
8 
{
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T 2000 700 5 10 1 1 0 6 1 1
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refdes=update_dr_o
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}
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C 2000 1100 1 0 0 in_port.sym
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{
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T 2000 1100 5 10 1 1 0 6 1 1
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refdes=update_dr_clk_o
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}
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C 2000 1500 1 0 0 in_port.sym
18 
{
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T 2000 1500 5 10 1 1 0 6 1 1
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refdes=test_logic_reset_o
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}
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C 2000 1900 1 0 0 in_port.sym
23 
{
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T 2000 1900 5 10 1 1 0 6 1 1
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refdes=tdo_i
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}
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C 2000 2300 1 0 0 in_port.sym
28 
{
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T 2000 2300 5 10 1 1 0 6 1 1
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refdes=tdi_pad_in
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}
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C 2000 2700 1 0 0 in_port.sym
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{
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T 2000 2700 5 10 1 1 0 6 1 1
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refdes=shift_dr_o
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}
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C 2000 3100 1 0 0 in_port.sym
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{
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T 2000 3100 5 10 1 1 0 6 1 1
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refdes=jtag_shift_clk
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}
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C 2000 3500 1 0 0 in_port.sym
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{
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T 2000 3500 5 10 1 1 0 6 1 1
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refdes=chip_id_tdo
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}
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C 2000 3900 1 0 0 in_port.sym
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{
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T 2000 3900 5 10 1 1 0 6 1 1
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refdes=capture_dr_o
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}
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C 2000 4300 1 0 0 in_port.sym
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{
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T 2000 4300 5 10 1 1 0 6 1 1
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refdes=aux_tdo_i
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}
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C 5800 300  1 0  0 out_port_vector.sym
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{
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T 6800 300 5  10 1 1 0 0 1 1
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refdes=chip_id_value[31:0]
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}
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C 5800 700  1 0 0 out_port.sym
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{
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T 6800 700 5  10 1 1 0 0 1 1
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refdes=tdi_o
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}
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C 5800 1100  1 0 0 out_port.sym
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{
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T 6800 1100 5  10 1 1 0 0 1 1
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refdes=shiftcapture_dr_o
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}
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C 5800 1500  1 0 0 out_port.sym
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{
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T 6800 1500 5  10 1 1 0 0 1 1
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refdes=shiftcapture_dr_clk_o
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}
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C 5800 1900  1 0 0 out_port.sym
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{
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T 6800 1900 5  10 1 1 0 0 1 1
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refdes=select_o
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}
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C 5800 2300  1 0 0 out_port.sym
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{
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T 6800 2300 5  10 1 1 0 0 1 1
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refdes=sample
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}
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C 5800 2700  1 0 0 out_port.sym
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{
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T 6800 2700 5  10 1 1 0 0 1 1
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refdes=next_tdo
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}
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C 5800 3100  1 0 0 out_port.sym
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{
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T 6800 3100 5  10 1 1 0 0 1 1
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refdes=jtag_reset
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}
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C 5800 3500  1 0 0 out_port.sym
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{
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T 6800 3500 5  10 1 1 0 0 1 1
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refdes=jtag_clk
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}
102 
C 5800 3900  1 0 0 out_port.sym
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{
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T 6800 3900 5  10 1 1 0 0 1 1
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refdes=extest
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}
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C 5800 4300  1 0 0 out_port.sym
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{
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T 6800 4300 5  10 1 1 0 0 1 1
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refdes=clamp
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}
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C 5800 4700  1 0 0 out_port.sym
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{
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T 6800 4700 5  10 1 1 0 0 1 1
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refdes=chip_id_select
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}
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C 5800 5100  1 0 0 out_port.sym
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{
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T 6800 5100 5  10 1 1 0 0 1 1
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refdes=bsr_select_o
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}
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C 5800 5500  1 0 0 out_port.sym
123 
{
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T 6800 5500 5  10 1 1 0 0 1 1
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refdes=aux_update_dr_o
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}
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C 5800 5900  1 0 0 out_port.sym
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{
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T 6800 5900 5  10 1 1 0 0 1 1
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refdes=aux_update_dr_clk_o
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}
132 
C 5800 6300  1 0 0 out_port.sym
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{
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T 6800 6300 5  10 1 1 0 0 1 1
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refdes=aux_test_logic_reset_o
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}
137 
C 5800 6700  1 0 0 out_port.sym
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{
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T 6800 6700 5  10 1 1 0 0 1 1
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refdes=aux_tdi_o
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}
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C 5800 7100  1 0 0 out_port.sym
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{
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T 6800 7100 5  10 1 1 0 0 1 1
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refdes=aux_shiftcapture_dr_clk_o
146 
}
147 
C 5800 7500  1 0 0 out_port.sym
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{
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T 6800 7500 5  10 1 1 0 0 1 1
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refdes=aux_shift_dr_o
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}
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C 5800 7900  1 0 0 out_port.sym
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{
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T 6800 7900 5  10 1 1 0 0 1 1
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refdes=aux_select_o
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}
157 
C 5800 8300  1 0 0 out_port.sym
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{
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T 6800 8300 5  10 1 1 0 0 1 1
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refdes=aux_jtag_clk
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}
162 
C 5800 8700  1 0 0 out_port.sym
163 
{
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T 6800 8700 5  10 1 1 0 0 1 1
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refdes=aux_capture_dr_o
166 
}

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