URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [classic_cmd_sync] - Blame information for rev 135

Details | Compare with Previous | View Log


 
 
   reg                    synced_shift_dr;
   reg                    synced_capture_dr;
 
 
 
 
reg   buffer;
 
always @(posedge shiftcapture_dr_clk or posedge test_logic_reset)
  if (test_logic_reset)                 buffer <= 1'b0;
  else
  if (select && capture_dr)             buffer <= 1'b1;
  else                                  buffer <= 1'b0;
 
 
 
 
   always@(posedge clk)
     if(!shiftcapture_dr_clk)
       begin
       synced_shift_dr    <= shift_dr ;
       synced_capture_dr  <= buffer ;
       end
 
     else
       begin
       synced_shift_dr    <= synced_shift_dr ;
       synced_capture_dr  <= synced_capture_dr ;
       end
 
 
 
 
   reg [1:0]  synced_shiftcapture_dr_clk;
 
 
   always@(posedge clk)
     synced_shiftcapture_dr_clk <= {synced_shiftcapture_dr_clk[0],shiftcapture_dr_clk};
 
 
 
   always@(posedge clk)
     if((select == 1'b0)||(buffer == 1'b0) )
       begin
       syn_capture_dr    <= 1'b0;
       end
     else
     begin
     if(synced_shiftcapture_dr_clk == 2'b01)
       begin
       syn_capture_dr    <= 1'b1 ;
       end
     else
       begin
       syn_capture_dr    <= 1'b0 ;
       end
     end
 
 
 
 
   reg [1:0]  synced_update_dr_clk;
 
 
   always@(posedge clk)
     synced_update_dr_clk <= {synced_update_dr_clk[0],update_dr_clk};
 
 
 
   always@(posedge clk)
     if(select == 1'b0)
       begin
       syn_update_dr    <= 1'b0;
       end
     else
     begin
     if(synced_update_dr_clk == 2'b01)
       begin
       syn_update_dr      <= 1'b1 ;
       end
     else
       begin
       syn_update_dr      <= 1'b0 ;
       end
     end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton
2
3			`reg synced_shift_dr;`
4			`reg synced_capture_dr;`
5
6
7
8
9			`reg buffer;`
10
11			`always @(posedge shiftcapture_dr_clk or posedge test_logic_reset)`
12			`if (test_logic_reset) buffer <= 1'b0;`
13			`else`
14			`if (select && capture_dr) buffer <= 1'b1;`
15			`else buffer <= 1'b0;`
16
17
18
19
20			`always@(posedge clk)`
21			`if(!shiftcapture_dr_clk)`
22			`begin`
23			`synced_shift_dr <= shift_dr ;`
24			`synced_capture_dr <= buffer ;`
25			`end`
26
27			`else`
28			`begin`
29			`synced_shift_dr <= synced_shift_dr ;`
30			`synced_capture_dr <= synced_capture_dr ;`
31			`end`
32
33
34
35
36			`reg [1:0] synced_shiftcapture_dr_clk;`
37
38
39			`always@(posedge clk)`
40			`synced_shiftcapture_dr_clk <= {synced_shiftcapture_dr_clk[0],shiftcapture_dr_clk};`
41
42
43
44			`always@(posedge clk)`
45			`if((select == 1'b0)\|\|(buffer == 1'b0) )`
46			`begin`
47			`syn_capture_dr <= 1'b0;`
48			`end`
49			`else`
50			`begin`
51			`if(synced_shiftcapture_dr_clk == 2'b01)`
52			`begin`
53			`syn_capture_dr <= 1'b1 ;`
54			`end`
55			`else`
56			`begin`
57			`syn_capture_dr <= 1'b0 ;`
58			`end`
59			`end`
60
61
62
63
64			`reg [1:0] synced_update_dr_clk;`
65
66
67			`always@(posedge clk)`
68			`synced_update_dr_clk <= {synced_update_dr_clk[0],update_dr_clk};`
69
70
71
72			`always@(posedge clk)`
73			`if(select == 1'b0)`
74			`begin`
75			`syn_update_dr <= 1'b0;`
76			`end`
77			`else`
78			`begin`
79			`if(synced_update_dr_clk == 2'b01)`
80			`begin`
81			`syn_update_dr <= 1'b1 ;`
82			`end`
83			`else`
84			`begin`
85			`syn_update_dr <= 1'b0 ;`
86			`end`
87			`end`
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [verilog/] [classic_cmd_sync] - Blame information for rev 135